DOWNLOAD Panasonic UF-7000 / UF-8000 / UF-7100 / UF-8100 (serv.man2) Service Manual ↓ Size: 2.44 MB | Pages: 127 in PDF or view online for FREE

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UF-7000 UF-8000 UF-7100 UF-8100 (serv.man2)
Pages
127
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2.44 MB
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Service Manual
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Device
Fax / FACSIMILE
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uf-7000-uf-8000-uf-7100-uf-8100-sm2.pdf
Date
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Panasonic UF-7000 / UF-8000 / UF-7100 / UF-8100 (serv.man2) Service Manual ▷ View online

9
SEPT 2005
Ver. 2.0
UF-7100/8100
UF-7000/8000
2.2.
Engine Control PC Board
2.2.1.
IC1 (ASIC)
(A) This block is the Serial Communication Interface with the Engine CPU (IC004).
(B) This block is the Stepping Motor Controller (CH1) to control the 2nd Feeder Motor.
(C) This block is the LSU Controller, and it consists of Laser Enable, Power Adjust and Video Data.
2.2.2.
Clock Circuit
The system clock (12.00MHz) is generated by IC002 and X001, and it is supplied to the CPU (IC006) and 
IC001.
nCS
SCLK
SDI
SD0
SM1A
 
nSM1EN
nLDEN
nADJUST
nVIDEO
LD5VSW
nRST
VDD
VSS
GND
nTRST
(A)
(B)
(C)
Chip Select
Serial Clock
Serial Input Data
Serial Output Data
Motor Clock 
Motor Enable
Laser Enable
Laser Power Adjust
Video Data Output
Power Supply Unit Detect
System Reset
+5V
CPU (IC006)
I/F
Stepping Motor
CH1 I/F
LSU I/F
IC001 (ASIC)
IC002 (Inverter)
11
10
X001
12.00 MHz
C115
C120
8
R158
C119
22
X0
IC006
(CPU)
R005
9
3
CLK1
IC001
(ASIC)
R159
10
SEPT 2005
Ver. 2.0
UF-7100/8100
UF-7000/8000
2.2.3.
Reset Circuit
Reset signal is generated when the power is turned On. The reset circuit initializes the CPU (IC006), the 
ASIC (IC001).
Approx. 100~800 msec after turning On the power, Pin4 of IC005 goes High.
19
6
nRST
IC006
IC001
R084
C083
C081
C079
3
4
1
2
IC005
VDD RESET
GND
CD
+
CPU
nRESET
ASIC
100-800 ms
5V
5V
0V
0V
VDD
(Pin2 of IC003)
RESET
(Pin4 of IC005)
Timing Chart
11
SEPT 2005
Ver. 2.0
UF-7100/8100
UF-7000/8000
2.2.4.
Main Motor Drive I/F Circuit
The Main Motor Control Signals are as follows:
Signal Name
Description
nMMCTL
This is the Main Motor Control Signal.
nMMLD
The Main Motor rotates 1908.35 or 954.18 rpm. This is a low level signal 
while the Motor rotates 1908.35 (or 954.18) rpm ± 6.25%.
nMMHALF
Main Motor rotation speed selection.
H: 1908.35 rpm, L: 954.18 rpm
R122
C099
R117
+5V
Q21
34
26
P26
P16
Q20
25
P27
IC006
(Engine CPU)
Main Motor
nMMCTL
nMMHALF
nMMLD
+24VIR
+24V
Front Cover Safety Interlock SW
CN017
1
3
6, 7
3
1
2
CN006
Engine Control PC Board
12
SEPT 2005
Ver. 2.0
UF-7100/8100
UF-7000/8000
2.2.5.
Laser Scanning Unit Control Circuit
The Laser Unit consists of Laser Drive Circuit and LSU Motor Drive Circuit.
Laser control signals are as follows.
nVIDEO:
This is actual data being printed.
nLDON:
When the nLDON signal is Low, the Laser Unit is activated.
When OPC Drum Unit is not installed, the Laser Unit is deactivated.
nHSYNC:
This is the horizontal synchronizing signal sent from the Timing Sensor (Laser Beam 
Detect Sensor) which detects the horizontal position of the Laser Beam across the 
drum.
nADJUST:
When the nADJUST signal is Low, APC (Auto Power Control) is activated.
nSNRCTL:
This is the LSU Motor Control Signal.
nSNRLD:
The PLL (Phase Locked Loop) maintains the LSU Motor speed at approx. 26K rpm.
When the SNRLD is Low, the LSU Motor rotates (approx. 26K rpm).
nSNRCLK:
This is the LSU Motor reference clock (approx. 2.6KHz).
nVIDEO
nLDON
nHSYNC
nADJUST
nVIDEO
nLDEN
nBD
nADJUST
Laser
Diode
LSU
Motor
Process 
Interlock SW
+5V (LD)
GND (+5V)
LSU
(Laser Scanning Unit)
Engine Control PC Board
IC001
(ASIC)
IC006
(Engine CPU)
+5V
GND (+5V)
GND(+24V)
48
50
5
36
30
R042
R043
R041
R040
+24V
GND (+24V)
nSNRCTL
nSNRLD
nSNRCLK
+24V
SNRCLK
SNRCTL
PUNIT
nSNRLD
R091
Q010
Q011
C088
C028
C1
14
C023
PPG02
P14
P52
P30
LD5VSW
R090
69
67
66
68
L023
C021
C018
R006
R028
C054
R038
R011
R015
R092
+5VSP
C093
C090
C089
IC009
C042
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