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13

SEPT 2005

Ver. 2.0

UF-7100/8100

UF-7000/8000

The fuser temperature is controlled by IC006 (Engine CPU). IC006 has an analog to digital (A/D) converter 
(AN0-AN7).
Thermistor TH is connected to IC006 (AN0). When IC006 (Pin31) is Low, Q009 is turned Off. And Q003 is 
turned On. Then Halogen Lamp in Fuser Unit is turned On.
When Front Cover is opened, the Front Cover Safety Interlock Switch is opened and the Halogen Lamp is 
turned Off.

Abnormal temperature detection circuit consists of the following 2 sub-sections.

1. Abnormally Low Temperature Detection

When abnormally low temperature is detected by IC006 (Engine CPU), the IC006 turns Off the 
Halogen Lamp.

2. Abnormally High Temperature Detection

When abnormally high temperature is detected by IC006 (Engine CPU), the IC006 turns Off the 
Halogen Lamp. If the Halogen Lamp is not turned Off by IC006 though the temperature of Halogen 
Lamp is abnormally high, the IC003 turns Off the Halogen Lamp electrically.

+5V

C069

C076

C077

R064

R070

R073

+24V +24VIR

R061

R062

GND (+24V)

R063

R077

R065

R066

TH

Front Cover 

Safety 

Interlock SW

GND (+5V)

THERMISTOR

IC006

(Engine CPU)

5
4

nDOPEN

2

17

P63

AN0

3

nFSRCTL

R081

PPG01

31

Q009

R072 R071

R067

R068

R076

R075

+24VIR

Q003

nFCTL

Halogen

Lamp

Drive

Circuit

LVPS

Unit

+

-

IC003

R161

R160

7
6

1

+

-

IC003

14

SEPT 2005

Ver. 2.0

UF-7100/8100

UF-7000/8000

This circuit consists of the DC-DC Converter, which boosts +24V to approx. +5.4kV (constant current 
approx. +300

µA) for the Charge Corona. The nCHGCTL signal controls the charge output. If the signal 

goes Low, the output is turned On.

When the charge circuit is activated (nCHGCTL signal is Low), this circuit is activated and approx. 
+900V is generated on the Grid.

When the charge circuit is activated (nCHGCTL signal is low), this circuit is activated. 
This voltage varies between +100V and +500V in accordance with the PWM (Pulse Width Modulation) 
signal nDB when the signal nDBCH is Low. Also approx. - 150V is generated when signal nDB and 
nDBCH is High.

This circuit consists of the DC-DC Converter, which boosts +24V to -700V ~ -6000V (constant current). 
This current varies between -4µA and -20µA in accordance with the PWM (Pulse Width Modulation) 
signal nTR when the signal nTRCTL is High.

This circuit consists of a DC-DC converter, which boosts +24V to +1500V. 
This voltage is generated when signal nTR is High and nTRCTL is Low.

1. Do not attempt to repair this Power Supply Unit. This Power Supply requires proper calibration after 
    any component replacement. Failure to do so may result in component damage, shock fire or other 
    hazard.
2. High Voltage is present on the PC Board. Use caution when measuring voltage levels.

15

SEPT 2005

Ver. 2.0

UF-7100/8100

UF-7000/8000

This machine has 2kbit EEPROM (IC007). Page Count Data, Calibration Data, etc. are saved on the IC.

The EEPROM control signals are explained as follows.

EEPCS:

This is the Chip select signal.

EEPCLK:

This is the Serial Data transfer clock.

EEPDO:

This is the Serial Data from CPU (IC006) to EEPROM (IC007).

EEPDI:

This is the Serial Data from EEPROM (IC007) to CPU (IC006).

CHGCTL

DBPWM

DBCH

TRPWM

TRCTL

4

1

CN008

6

5

8

7

9

2,3

nCHGCTL

+24VIR

nDB

nDBCH

nTR

nTRCTL

+5V

GND (+24V)

7

10

CN501

5

6

3

4

2

8,9

Charge Control
Circuit

Transformer

Dev. Bias Control
Circuit

Transformer

Transformer

Transfer 
Control
Circuit

Transfer Roller 
Cleaning
Control Circuit

Transfer 

Dev. Bias

Charge

OPC

Grid 
Control
Circuit

Grid 

+24VIR

+24V

Process
Interlock
SW

+5VSP

+5VSP

+5VSP

+5V

+5V

R078

R080

R079

8

54

9

58

10

IC006

(Engine CPU)

Q002

Q001

Q006

Q005

L007

L010

L008

L009

L006

Q007

27

3 DI

IC007 (EEPROM)

IC006 (CPU)

EEPDO

EEPDO

33

4 DO

EEPDI

EEPDI

29

1 CS

EEPCS

EEPCS

28

2 SK

EEPCLK

EEPCLK

R094

R093

16

SEPT 2005

Ver. 2.0

UF-7100/8100

UF-7000/8000

This machine has two safety interlock switches: Front Cover Safety Interlock Switch, and the Process 
Interlock Switch. +24V power is supplied to the Front Cover Safety Interlock Switch. When the Front Cover 
is opened, the Front Cover Safety Interlock Switch is opened and shuts Off the Main Motor Power and the 
High Voltage Unit Power. As a result, the comparator output at Pin2 of IC003 is changed from a high level to 
a low level. IC006 (CPU) receives this signal and turns Off the main motor control signal, the Laser 
Scanning Unit, etc. When the OPC Drum Unit is not installed, the Process Interlock Switch is opened and 
shuts Off the +5V power for the Laser Diode. IC006 (CPU) and IC001 (ASIC) receive this +5V power 
condition and turn Off the main motor control signal, the laser control signals, etc.

Front Cover Safety 

Interlock Switch

Process 

Interlock Switch

IC006

(CPU)

IC001 (ASIC)

+5V

+24V

CN006

1
2
3

CN003

1
2
3

R077

IC003

+5V

R061

R062

GND (24V)

GND (5V)

R042

R041

R043

R065

R066

+5V

+5V (LD)

(Laser Diode Power)

5
4

+
-

2

17

50

48

+24VIR

Main Motor Power
High Voltage Unit Power 

(                                )

R063

nDOPEN

P63

P30

GND

(24V)

C033

C054

GND (5V)