DOWNLOAD Panasonic UF-6300 / UF-6200 / UF-5300 (serv.man3) Service Manual ↓ Size: 5.4 MB | Pages: 117 in PDF or view online for FREE

13

     

UF-6300/6200/5300

     

The image data read by the optical unit is input to the CCD mounted on the CCD PC Board, then 
transferred to the SC PC Board after the optical information is converted into an electrical signal by the 
CCD. The following shows a block diagram of the picture signal scanning circuit. This picture signal 
scanning circuit consists of (1) ABC circuit, (2) shading correction circuit, (3) offset control circuit, (4) picture 
signal binary coding correction circuit and (5) reducing circuit.

This circuit consists of IC28, IC30, C175, R288 and R285. Its function is to prevent deterioration of 
picture quality due to dirt on the document or degrading of the luminous energy of the Xenon Lamp light 
source. The picture signal from the CCD is amplified in IC28 and input to IC30, where it is converted 
from analog to digital and the shading is corrected. When the signal exceeds +5V as the result of this 
amplification and correction, capacitor C175 is charged through R288. This charging voltage lowers the 
level of the picture signal input to IC28. When the picture signal voltage rises, this charge voltage 
becomes higher. When the picture signal level lowers due to the background color, etc., of a transmitting 
document, the voltage of the charged capacitor C175 is discharged through R285. Consequently, the 
output of the ABC circuit is kept constant to maintain the picture quality, regardless of changes in the 
CCD output level.

W

B

1728 bit

CCD

PD3753

Differential

Amplifier

CCD PC Board

SC PC Board

CCD

Drive

Circuit

Delay

[SC]
IC30
MN86075

IC3
DZAC000273

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UF-6300/6200/5300

     

The Shading Correction Circuit, included in IC30, is provided to correct for reduction in LED lamp 
intensity around the optical lens and LED lamp intensity distortion due to shading of each bit. This circuit 
scans the white reference on the transmitting document plate immediately before the document reaches 
the scanning position and writes a compensation value according to the distortion of the waveform, at 
the time, into the S-RAM (IC31).When the actual picture signal is input, the circuit corrects the picture 
signal shading, according to this compensation value. This shading is carried out for each page during 
transmission or copy.

The Offset Control Circuit consists of IC44, IC30 and IC28, and controls the black level of the CCD 
output to be at 0V by using the input.

The Picture Signal Binary Coding Correction Circuit is included in IC30. It is used to obtain a binary 
coding signal which is a corrected picture and error diffused signal of a false halftone signal, which is 
detected from a shaded picture signal.

This circuit is also contained in IC30. Its function is to generate FSG, FCK1, FCK2 clock signals, which are 
required for driving the CCD. These clock signals are generated by the system clock generator circuit 
derived from the 8 MHz clock signal that is input to IC30. Its timing chart is shown below. The FR signal is 
input to the IC3 for synchronizing the IC30 and IC3.

CCD Output

ABC Circuit Output

R288

C175

R285

IC28, 1

IC28, 2

32

37

19

41

39

40

IC30

Control

Circuit

OS

0V

3V

0V

IC44

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UF-6300/6200/5300

     

The Line Monitor Circuit consists of an operational  DAA (The secondary side chip) and its peripheral 
circuits. Its function is to monitor the dial tone, DTMF tone, response signals, etc. over the speaker. It also 
sounds the output of the key touch tones, alarm tones, etc. from the panel CPU over the speaker. The 
Received Signals are output from DAA of Secondary circuit, and through Analog AGC, Electronic Volume, 
Amplifier and over the speaker.
The monitor tone from the phone line and the buzzer tone from the panel can be adjusted from the Control 
Panel.

The transmit motor is a PM type, two-phase bi-polar motor. The stepping signal and chopping current 
control signals (pTAPH, pTBPH, pTA10, pTA11, pTB10 and pTB11) are sent to the chopper drive circuit, 
comprised of IC36, IC37 and its peripheral circuitry, from IC3 SHINE output port. The motor is powered by 
+24 VDC and is driven by a 1/2-phase excitation, and greater step division is provided by controlling the 
phase circuit in steps (micro-step control).

FCK1

FCK2

FSG

CCD

FCK1
FCK2

FSG

IC3

SHINE

IC30

86075

FR

Volume

Control

Circuit
(IC21)

Level Control

Circuit

(Q3)

(IC20, 2)

Speaker

Amplifier

(Q4,5)

Speaker

Line Monitor Signal

(from AGC Circuit)

Buzzer Clock

(from Control Panel Unit)

Buzzer Tone Switch

(from Output Port)

+

-

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UF-6300/6200/5300

     

The Line Control Circuit consists of CML relay, DP circuit, DAA (Direct Access Arrangement), Ring Detect 
Circuit for power-save and DC hold circuit. A Jack for an external telephone, which can be used for  either 
an external telephone or an optional Handset Kit. The block diagram of the Line Control Circuit is shown 
below.

Tx Stepper
Motor

Tx Motor Driver Circuit Block Diagram

SHINE

IC3

Motor

Driver

IC36

+24V

Motor

Driver

IC37

+24V

R371

R370

DP Control

Ringer Signal Detection,

TAM I/F,

DTMF Remote Detection

Off-Hook

Detection

Speech

IC

DAA

Line

I/F

Si3019

(IC23)

DP

Circuit

DC Hold

Circuit

Ring Signal

Detector

for Wake-up

(PC301)

Ringer

IC

+
-

~
~

Hook SW

External

External

Telephone

Telephone

Jack

Connect either one

Line

CML Relay

Optional Handset Kit

+
-

~
~

DAA

Control

I/F

Si3056

MODEM

MMD5020

CPU

IC3

SHINE

PNL

Line Control Circuit

MJR3 PCB

SC PCB

(IC24)