Panasonic UF-6300 / UF-6200 / UF-5300 (serv.man3) Service Manual / Other ▷ View online
25
UF-6300/6200/5300
LVPS
Input Circuit
AC line voltage travels to the rectifying circuit through the line filter. The line filter eliminates RFI noise
which may otherwise pass to the AC line from the power supply unit. It also protects the power supply
unit from transient noise which may pass into the unit from the AC line.
which may otherwise pass to the AC line from the power supply unit. It also protects the power supply
unit from transient noise which may pass into the unit from the AC line.
Rectifying Circuit
AC power is rectified by D100 and charges C103 to make high DC voltage, then supply power to
converter circuit.
Kick-on voltage for control IC (IC105) is supplied AC power through R134, R135 and R136.
Inrush current is limited by TH100.
converter circuit.
Kick-on voltage for control IC (IC105) is supplied AC power through R134, R135 and R136.
Inrush current is limited by TH100.
Converter Circuit
A IC (IC105), in combination with transformer T100, form a switching power supply circuit using the RCC
(Ringing Choke Converter) system.
As soon as power is applied to the Power Supply Unit, AC line voltage is rectified by D100 and is
smoothed by capacitor C103. The protection circuit at the time of start-up is controlled by an IC (IC105)
and resistors R134, R135 and R136.
(Ringing Choke Converter) system.
As soon as power is applied to the Power Supply Unit, AC line voltage is rectified by D100 and is
smoothed by capacitor C103. The protection circuit at the time of start-up is controlled by an IC (IC105)
and resistors R134, R135 and R136.
Main Switching Circuit
In the above circuit, when the main switching transistor, Q100, is turned On, input voltage, Ei, is supplied
to the primary winding of transformer T100. However, no current will flow through diode D102 of the
secondary side, due to reverse polarity of the secondary winding causing no current flow within T100.
But the transformer charges with energy. When Q100 is turned Off, the supply voltage to the primary
winding shuts off and the windings of T100 change polarity, allowing D102 to conduct, releasing the
energy accumulated in T100 to the circuit. When the energy is discharged through D102, Q100 turns on,
once again reversing the polarity on T100 windings, creating a self-oscillation circuit.
to the primary winding of transformer T100. However, no current will flow through diode D102 of the
secondary side, due to reverse polarity of the secondary winding causing no current flow within T100.
But the transformer charges with energy. When Q100 is turned Off, the supply voltage to the primary
winding shuts off and the windings of T100 change polarity, allowing D102 to conduct, releasing the
energy accumulated in T100 to the circuit. When the energy is discharged through D102, Q100 turns on,
once again reversing the polarity on T100 windings, creating a self-oscillation circuit.
Ei
Eo
D102
P --- Primary Winding
S --- Secondary Winding
B --- Control Winding
S --- Secondary Winding
B --- Control Winding
T100
Q100
P
B
Control Circuit
S
+
26
UF-6300/6200/5300
In the actual circuit, the fixed output voltages are obtained by changing the winding ratio of transformer
T100. In this converter circuit, the output voltages are stabilized by controlling the duty cycle of the ON
and OFF timing of the transistor. In this power supply, the bias winding is built into the transformer. The
power supply has four outputs, +24 VDC, -5 VDC, +5 VP and +5 VDC. The +24 VDC output is protected
by the Error Detection Circuit, and the +5VDC, +5 VP and -5 VDC outputs are protected by the circuitry
inside of the voltage regulator IC.
T100. In this converter circuit, the output voltages are stabilized by controlling the duty cycle of the ON
and OFF timing of the transistor. In this power supply, the bias winding is built into the transformer. The
power supply has four outputs, +24 VDC, -5 VDC, +5 VP and +5 VDC. The +24 VDC output is protected
by the Error Detection Circuit, and the +5VDC, +5 VP and -5 VDC outputs are protected by the circuitry
inside of the voltage regulator IC.
Control Circuit and Error Detection Circuit
The control circuit amplifies the output of the duty cycle according to the error voltage detected by the
Error Detection Circuit, and drives the main transistor Q100. The method used to change the duty cycle
is to change the ON time period. When the output voltage of the +24 VDC circuit rises, the current of
photo coupler PC103 increases, the output pulse width of the control circuit decreases and the ON time
period of Q100 decreases. This control circuit decides the minimum OFF time period by itself. When the
oscillation frequency becomes higher and the OFF time period becomes minimum, the OFF time period
remains unchanged and only the ON time period decreases. This way, there is a upper limit of the
oscillation frequency and the duty cycle is expanded.
Error Detection Circuit, and drives the main transistor Q100. The method used to change the duty cycle
is to change the ON time period. When the output voltage of the +24 VDC circuit rises, the current of
photo coupler PC103 increases, the output pulse width of the control circuit decreases and the ON time
period of Q100 decreases. This control circuit decides the minimum OFF time period by itself. When the
oscillation frequency becomes higher and the OFF time period becomes minimum, the OFF time period
remains unchanged and only the ON time period decreases. This way, there is a upper limit of the
oscillation frequency and the duty cycle is expanded.
Over Current Limiter (O.C.L)
The +24 VDC output is limited by Ton MAX Limiter (ON time period of transistor Q100) which is part of
the control circuit. The +5 VP, -5 VDC and +5 VDC outputs have over current limiters provided inside the
voltage regulator.
the control circuit. The +5 VP, -5 VDC and +5 VDC outputs have over current limiters provided inside the
voltage regulator.
The value of output voltage is
Eo=d/(1-d)*Ei
d=Ton/Ts
Equivalent circuit model for the RCC.
Ton : ON time of Q100
In the equivalent circuit when SW is ON, current flows
SW L
When SW is OFF, current flows
L D RL
The value of inductance increase current between
ON period. (d*Ts)
IL=Ei/L*d*Ts . . . . . . . . . . . . . . . . . .(1)
The value of inductance decrease current between
OFF period. ((1-d)*Ts) . . . . . . . . . . . . . . . .(2)
From equation (1) and (2),
E0=d/(1-d)*Ei
SW L
When SW is OFF, current flows
L D RL
The value of inductance increase current between
ON period. (d*Ts)
IL=Ei/L*d*Ts . . . . . . . . . . . . . . . . . .(1)
The value of inductance decrease current between
OFF period. ((1-d)*Ts) . . . . . . . . . . . . . . . .(2)
From equation (1) and (2),
E0=d/(1-d)*Ei
Ts : Period of oscillation
VL
VL
L
C
T100
D(D102)
Eo
Eo
Ts
dTs
RL
Ei
SW
(Q100)
T
IL
Ei
(1-d)Ts
dTs
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UF-6300/6200/5300
1.1.14 LAN Control Circuit (Option)
LAN Controller
1. LAN Controller (IC1)
This conforms to IEEE 802.3 Ethernet Controller. The CPU (SC PCB) bus is directly connected and the
data interrupt is controlled by pLANINT. The 25 MHz clock is supplied by X1. The LAN Controller for
the system timing clock divides the frequency provided from X1. The clock signal is also supplied for
the Manchester encoding/decoding circuit for data conversion.
The LAN Controller is a mixed signal Analog/Digital device that implements the MAC and PHY portion
of the CSMA/CD protocol at 10 and 100Mbps.
The LAN controller contains a built in 8 KByte RAM for transmission and reception buffer.
data interrupt is controlled by pLANINT. The 25 MHz clock is supplied by X1. The LAN Controller for
the system timing clock divides the frequency provided from X1. The clock signal is also supplied for
the Manchester encoding/decoding circuit for data conversion.
The LAN Controller is a mixed signal Analog/Digital device that implements the MAC and PHY portion
of the CSMA/CD protocol at 10 and 100Mbps.
The LAN controller contains a built in 8 KByte RAM for transmission and reception buffer.
2. EEPROM (IC2)
This memory stores the configuration registers and MAC (Media Access Control) address for the LAN
controller. Data is transferred to LAN controller (serial transfer) when the power is turned "On". The
MAC address for the LAN controller represents the location on the LAN.
controller. Data is transferred to LAN controller (serial transfer) when the power is turned "On". The
MAC address for the LAN controller represents the location on the LAN.
3. Ethernet Interface (RJ45 Connector)
Provides the 10Base-T/100Base-TX Ethernet interface.
Two LED (LINK and Activity) and Transformer module are in the RJ45 Connector.
Two LED (LINK and Activity) and Transformer module are in the RJ45 Connector.
a. LINK LED
The LINK LED normally illuminates when the LAN cable is connected and when a link pulse is
detected. Consequently, LED can be used to determine whether the 10Base-T/100Base-TX cable
has become disconnected (RX side).
detected. Consequently, LED can be used to determine whether the 10Base-T/100Base-TX cable
has become disconnected (RX side).
b. Activity LED
This LED illuminates when reception data is present on the LAN. (The LED also illuminates when
reception data for other devices is present.)
reception data for other devices is present.)
CPU
V850E/MA1
(IC1)
SHINE
DZAC000273
(IC3)
FROM 4MB
Program
(IC9)
FROM 8MB
Image Memory
(IC10)
MN86075
(IC30)
MODEM
MMD5020
(IC22)
DAA
Si3056,
Si3019
(IC23, 24)
D-BUS
Laser Printer
CCD PCB
Line
Line
Memory
Page
Memory
ECM
Buffer
S-DRAM 8MB
(IC7)
LAN
Controller
(IC1)
RJ45
LINK
RX
INTERNET
(10Base-T/100Base-TX)
(10Base-T/100Base-TX)
LAN PCB
EEP
ROM
(IC2)
25MHz
X1
(1)
(2)
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UF-6300/6200/5300
Signal Routing
1. LAN Transmission
a. Transfers the MMR coded data from Image Memory (FROM) to CPU (SC PCB) and converts the
MH coded data.
b. Transfer the MH coded data of CPU (SC PCB) to SDRAM.
c. Transfer the converted text data to buffer RAM on LAN controller (LAN PCB) sequentially.
d. The transmission packet is processed by FIFO transfer to buffer RAM and then converted for
Manchester code. Finally, they are converted for differential pair signal and transmitted to Internet.
2. LAN Reception
a. Processed received data for Manchester coded signal at LAN controller.
b. The decoded received packet goes to buffer RAM through the FIFO. The data stored in buffer RAM
b. The decoded received packet goes to buffer RAM through the FIFO. The data stored in buffer RAM
is transferred to SDRAM (SC PCB) by requests from SC PCB.
c. Decodes the Base 64 for MH coded image data at SDRAM and transfers CPU (SC PCB).
d. Inputs MMR coded data from CPU transfers Image Memory (FROM).
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