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This 512KB ROM (FLASH MEMORY) carries a common area of 32KB and bank areas which each have 8KB (BK4~BK63). The
addresses from 0000H to 7FFFH are for the common area and from 8000H to 9FFFH are for the bank areas.

The DRAM serves as CPU and receives memory.
The address is F200H~F3FFH (DRAM access window 1) and F600H~F7FFH (DRAM access window 2).

The output signal (reset) from pin 4 of the voltage detect IC (IC3) is input to the ASIC (IC1) 114 pin.

1. During a momentary power interruption, a positive reset pulse of 50~70 msec is generated and the system is reset  com-

pletely.

2. The watch dog timer, built-in the ASIC (IC1), is initialized by the CPU about every 1.5 ms.

When a watch dog error occurs, pin 115 of the ASIC (IC1) becomes low level.
The terminal of the 'WDERR' signal is connected to the reset line, so the 'WDERR' signal works as the reset signal.

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1. Function

This unit has a lithium battery (BAT1) which works for the Real Time Clock (RTC, Integrated into ASIC:IC1).
The RTC continues functioning, even when the power switch is OFF, backed up by a lithium battery.

2. Circuit Operation

When the power is turned ON, power is supplied to RTC (IC1). 
At this time, the voltage at pin 14 of RTC (IC1) is +3.3V. When the power is turned OFF, the battery supplies the power to
RTC through J1, R80, D503. At that time, the voltage at pin 14 of IC1 are about +2.5V. When the power is OFF and the +5V
and +3.3V voltages decrease, the LOW is input to pin 114 of IC1. Pin 111 of IC1 outputs the reset signals. Pin 11 of IC1
become low, then RTC (IC1) go into the back up mode, when the power consumption is lower.

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1. Function 

 The thermistor changes the resistor according to the temperature and uses the thermistor's characteristics. The output of pin
139 of IC1 becomes a low level. Then when it becomes a high level, it triggers point A. In point C, according to the voltage
output time, the thermal head's temperature is detected.
 After the thermal head temperature is converted to voltage in B, it is then changed to digital data in the A/D converter inside
IC1. The CPU decides the strobe width of the thermal head according to this value. Therefore, this circuit can keep the ther-
mal head at an even temperature in order to stabilize the printing density and prevent the head from being overheated.

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1. Line information is read by CIS (to be used as the reference white level) via route (1), and is input to IC1. Refer to Block Dia-

2. In IC1, the data is adjusted to a suitable level for A/D conversion in the Analog Signal Processing Section, and via route (2) it

is input to A/D conversion (8 bit). After finishing A/D conversion, the data is input to the Image Processing Section via route
(3). Then via route (4) and route (5), it is stored in RAM as shading data.

3. The draft’s information that is read by CIS is input to IC1 via route (1). After it is adjusted to a suitable level for A/D conversion

via route (2), the draft’s information is converted to A/D (8 bit), and it is input to the Image Processing Section. The other side,
the shading data which flows from RAM via route (6) and route (7), is input to the Image Processing Section. After finishing
the draft’s information image processing, white is regarded as "0" and black is regarded as "1". Then via routes (4) and (5),
they are stored in RAM.

4. The white/black data stored as above via routes (6) and (8) is input to the P/S converter. The white/black data converted to

serial data in the P/S converter is input to the Thermal Head via route (9) and is printed out on recording paper.
Note:

Fine: Reads 3.85 lines/mm 
Super Fine: Reads 7.7 lines/mm
Photo: Reads 15.4 lines/mm

1. Same processing as Copy items 1 - 3.
2. The data stored in the RAM of IC1 is output from IC1 via routes (6) and (10), and is stored in the system bus. 

Via route (11), it is stored in the communication buffer inside DRAM (IC4).

3. While retrieving data stored in the communication buffer synchronous with the modem, the CPU (inside IC1) inputs the data to

the modem along route (12), where it is converted to serial analogue data and forwarded over the telephone lines 

via 

the

NCU Section.

1. The serial analog image data is received over the telephone lines and input to the modem via the NCU section, where it is

demodulated to parallel digital data. Then the CPU (IC1) stores the data in the communication buffer DRAM (IC4) along route
(11).

2. The data stored in DRAM (IC4) is decoded by the CPU (IC1) via route (12), and is stored in RAM via routes (13) and (5).
3. Same processing as Copy item 4.