Panasonic KX-FT78RU-B / KX-FT78RU-W Service Manual ▷ View online
5.3.2.
ASIC (IC1)
This custom IC is used for general FAX operations.
1. CPU
This model uses a Z80 equivalent CPU operating at 8MHz.
Many of the peripheral functions are handled by custom designed LSIs. As a result, the CPU only needs to process the result.
Many of the peripheral functions are handled by custom designed LSIs. As a result, the CPU only needs to process the result.
2. RTC
Real time clock.
3. DECODER
Decodes the address.
4. ROM/RAM I/F
Controls the SELECT signal of ROM or RAM and bank switching.
5. CIS I/F
Controls document reading.
6. IMAGE DATA RAM
This is inside the ASIC and has 8KB which is used for image processing.
7. THERMAL HEAD I/F
Transmits the recorded data to the thermal head.
8. MOTOR I/F
Controls the motor which feeds the document and feeds the reading document.
9. OPERATION PANEL I/F
Control port for Operation Panel.
10. I/O PORT
I/O Port Interface (for analog board port control).
11. ANALOG BLOCK
Electronic volume for the handset and TAM monitor.
Sends beep tones, etc.
Sends beep tones, etc.
Descriptions of Pin Distribution (IC1)
NO
SIGNAL
I/O
POWER SUPPLIED
VOLTAGE
DESCRIPTION
1
AIN1
A
3.3V
CCD IMAGE SIGNAL INPUT
2
AIN2
A
3.3V
THERMISTOR TEMPERATURE WATCH INPUT
3
AIN3
A
3.3V
4
AMON
A
3.3V
ANALOG SIGNAL MONITOR TERMINAL
5
VSSB
GND
POWER SOURCE (ANALOG GND)
6
VDDB
3.3V
POWER SOURCE (ANALOG 3.3V)
7
VDD(3.3V/B)
3.3V/BATT
POWER SOURCE (+3.3V/LITHIUM BATTERY)
8
X32OUT
O
3.3V/BATT
RTC (32.768KHz) CONNECTION
9
X32IN
I
3.3V/BATT
RTC (32.768KHz) CONNECTION
10
VSS
GND
GND
11
XBACEN
I
5V/BATT
BACKUP ENABLE
12
VDD(5V/B)
5V/BATT
POWER SOURCE (+5V/LITHIUM BATTERY)
13
XRAMCS
O
5V/BATT
RAM (IC4) CHIP SELECT
14
FTG
O
5V
SH SIGNAL OUTPUT FOR CIS (SI)
15
F1
O
5V
01SIGNAL OUTPUT FOR CIS(CLK)
16
F2/OP
O
5V
OUTPUT PORT (LED ON)
17
FR/OP
O
5V
ACK (DTMF RECEIVER CONTROL)
18
CPC
I
5V
INPUT PORT (CPC)
19
VDD(5V)
5V
POWER SOURCE (+5V)
20
VSS
5V
POWER SOURCE (GND)
21
RVN
I
5V
INPUT PORT (CISSEL)
22
IRDATXD/IOP
I
5V
INPUT PORT (JAM)
23
IRDARXD/IOP80
O
5V
OUTPUT PORT (H/S MUTE)
24
TXD/IOP
O
5V
OUTPUT PORT
25
RXD/IOP
O
5V
OUTPUT PORT (TELRXENB)
26
XRTS/IOP
O
5V
OUTPUT PORT (P-SHORT)
27
XCTS/IOP
O
5V
OUTPUT PORT (MDMTXENB)
28
MIDAT/IOP
O
5V
OUTPUT PORT (TONE1ENB)
105
KX-FT78RU-B / KX-FT78RU-W
NO
SIGNAL
I/O
POWER SUPPLIED
VOLTAGE
DESCRIPTION
29
MICLK/IOP
O
5V
OUTPUT PORT (TONE2ENB)
30
TONE1
A
5V
TONE OUTPUT
31
TONE2
A
5V
TONE OUTPUT
32
VOLUREF
A
5V
ANALOG REF VOLTAGE
33
VOLUOUT
A
5V
VOLUME OUTPUT
34
VOLUIN
A
5V
VOLUME INPUT
35
MILAT/IOP
O
5V
OUTPUT PORT (H/S RXENB)
36
XNMI
I
5V
HIGH FIXED
37
FMEMDO/IOP
O
5V
ALE (FLASH MEMORY CONTROL)
38
FMEMDI/IOP
O
5V
FLASH MEMORY (IC6) CHIP SELECT
39
FMEMCLK/IOP
I
5V
INPUT PORT (BELL) R/B (FLASH MEMORY
CONTROL)
CONTROL)
40
VSS
GND
POWER SOURCE (GND)
41
VDD(5V)
5V
POWER SOURCE (+5V)
42
20KOSC/IOP
O
5V
CLE (FLASH MEMORY CONTROL)
43
XWAIT
I
5V
INPUT PORT (HOOK)
44
HSTRD/IOP
O
5V
FRD (FLASH MEMORY RD)
45
HSTWR/IOP
O
5V
FWR (FLASH MEMORY WR)
46
XOPRBE
O
5V
OUTPUT PORT (SP-MUTE)
47
ADR15
O
5V
CPU ADDRESS BUS 15 (NOT USED)
48
ADR14
O
5V
CPU ADDRESS BUS 14 (NOT USED)
49
ADR13
O
5V
CPU ADDRESS BUS 13 (NOT USED)
50
VDD(3.3V)
3.3V
POWER SOURCE (+3.3V)
51
XOUT
O
3.3V
SYSTEM CLOCK (24MHz)
52
XIN
I
3.3V
SYSTEM CLOCK (24MHz)
53
VSS
GND
POWER SOURCE (GND)
54
VDD(5V)
5V
POWER SOURCE (+5V)
55
XTEST
O
5V
24MHz CLOCK
56
TEST1
I
5V
HIGH FIXED
57
TEST2
I
5V
HIGH FIXED
58
TEST3
I
5V
HIGH FIXED
59
TEST4
I
5V
HIGH FIXED
60
XMDMINT
I
5V
MODEM INTERRUPT
61
XMDMCS
O
5V
MODEM (IC5) CHIP SELECT
62
VSS
GND
POWER SOURCE (GND)
63
VDD(3.3V)
3.3V
POWER SOURCE (+3.3V)
64
XRAS/IOP
O
5V
MODEM RESET
65
XCAS1/IOP
O
5V
SD (Serial Data from DTMF Receiver)
66
XCAS2/IOP
I
5V
INPUT PORT (BELL)
67
XRESCS2
O
5V
OPRESET
68
DB3
I/O
5V
CPU DATA BUS 3
69
DB2
I/O
5V
CPU DATA BUS 2
70
DB4
I/O
5V
CPU DATA BUS 4
71
DB1
I/O
5V
CPU DATA BUS 1
72
DB5
I/O
5V
CPU DATA BUS 5
73
DB0
I/O
5V
CPU DATA BUS 0
74
DB6
I/O
5V
CPU DATA BUS 6
75
VSS
GND
POWER SOURCE (GND)
76
VDD (3.3V)
3.3V
POWER SOURCE (+3.3V)
77
DB7
I/O
5V
CPU DATA BUS 7
78
XROMCS
I/O
5V
ROM (IC2) CHIP SELECT
79
RD
O
5V
CPU RD
80
WR
O
5V
CPU WR
81
VSS
GND
POWER SOURCE (GND)
82
VDD (5V)
5V
POWER SOURCE (+5V)
83
ADR0
O
5V
CPU ADDRESS BUS 0
84
ADR1
O
5V
CPU ADDRESS BUS 1
85
ADR2
O
5V
CPU ADDRESS BUS 2
86
ADR3
O
5V
CPU ADDRESS BUS 3
87
ADR4
O
5V
CPU ADDRESS BUS 4
88
ADR5
O
5V
CPU ADDRESS BUS 5
89
ADR6
O
5V
CPU ADDRESS BUS 6
90
ADR7
O
5V
CPU ADDRESS BUS 7
91
ADR8
O
5V
CPU ADDRESS BUS 8
92
ADR9
O
5V
CPU ADDRESS 9
93
ADR10
O
5V
CPU ADDRESS 10
106
KX-FT78RU-B / KX-FT78RU-W
NO
SIGNAL
I/O
POWER SUPPLIED
VOLTAGE
DESCRIPTION
94
ADR11
O
5V
CPU ADDRESS 11
95
ADR12
O
5V
CPU ADDRESS 12
96
VSS
GND
POWER SOURCE (GND)
97
VDD (5V)
5V
POWER SOURCE (+5V)
98
RBA0
O
5V
ROM/RAM BANK ADDRESS 0
99
RBA1
O
5V
ROM/RAM BANK ADDRESS 1
100
RBA2
O
5V
ROM/RAM BANK ADDRESS 2
101
RBA3
O
5V
ROM/RAM BANK ADDRESS 3
102
RBA4
O
5V
ROM/RAM BANK ADDRESS 4
103
RBA5
O
5V
ROM/RAM BANK ADDRESS 5
104
RBA6/IOP96
I
5V
INPUT PORT (PAPER)
105
STB1
O
5V
STROBE SIGNAL OUTPUT TO THERMAL HEAD
106
STB2
O
5V
STROBE SIGNAL OUTPUT TO THERMAL HEAD
107
STB3
O
5V
STROBE SIGNAL OUTPUT TO THERMAL HEAD
108
XRESET
I
5V
RESET INPUT
109
XORESET
O
5V
RESET OUTPUT
110
VDD (5V)
5V
POWER SOURCE (+5V)
111
VSS
GND
POWER SOURCE (GND)
112
XRESET1
I
5V
RESET INPUT
113
WDERR
O
5V
WATCHED ERROR OUTPUT SIGNAL
114
THDAT
O
5V
RECORDED IMAGE OUTPUT
115
THCLK
O
5V
CLOCK OUTPUT FOR DATA TRANSFER
116
VDD (3.3V)
3.3V
POWER SOURCE (3.3V)
117
VSS
GND
POWER SOURCE (GND)
118
THLAT
O
5V
PULSE OUTPUT FOR DATA LATCH
119
STBNP
I
5V
INPUT PORT (MOTOR POS.)
120
RM0/IOP
O
5V
MOTOR CONTROL (D)
121
RM1/IOP
O
5V
MOTOR CONTROL (C)
122
RM2/IOP
O
5V
MOTOR CONTROL (B)
123
RM3/IOP
O
5V
MOTOR CONTROL (A)
124
RXE/IOP
O
5V
MOTOR ENABLE SIGNAL
125
TMO
O
5V
OUTPUT PORT (THON)
126
VDD (5V)
5V
POWER SOURCE (+5V)
127
VSS
GND
POWER SOURCE (GND)
128
TM1/IOP
I
5V
OUTPUT PORT
129
TM2/IOP
I
5V
INPUT PORT (CIS ON)
130
TM3/IOP
O
5V
OUTPUT PORT (RLY)
131
TXE/IOP
I
5V
INPUT PORT (CUT. POS.)
132
KSTART
O
5V
OPERATION PANEL CONTROL
133
KLATCH
O
5V
OPERATION PANEL CONTROL
134
KSCLK
O
5V
OPERATION PANEL CONTROL
135
KTXD
O
5V
OPERATION PANEL CONTROL
136
KRXD
I
5V
OPERATION PANEL CONTROL
137
ADSEL1
O
5V
CHANNEL SELECT SIGNAL FOR AIN2
138
VSSC
GND
POWER SOURCE (ANALOG GND)
139
VDDC
3.3V
POWER SOURCE (ANALOG +3.3V)
140
VSSA
GND
POWER SOURCE (ANALOG GND)
141
VDDA
3.3V
POWER SOURCE (ANALOG +3.3V)
142
VREFB
A
3.3V
A/D CONVERTER´S ZERO STANDARD VOLTAGE
OUTPUT
OUTPUT
143
VCL
A
3.3V
ANALOG PART STANDARD VOLTAGE SIGNAL
144
VREFT
A
3.3V
A/D CONVERTER´S FULL SCALE VOLTAGE
OUTPUT
OUTPUT
107
KX-FT78RU-B / KX-FT78RU-W
5.3.3. ROM (IC2)
This 512 KB ROM (OTPROM or MASKROM) has 32 KB of common area and bank area (BK4~BK 63).
The capacity of each bank is 8 KB.
The addresses of the common area are from 0000H to 7FFFH, and addresses 8000H to 9FFFH are for the bank area.
5.3.4. RAM (IC4)
This 32 KB RAM has 8 KB of common area and bank area (BK0, BK1).
The capacity of each bank is 12 KB.
The addresses of the common area are from D000H to EFFFH, and addresses A000H to CFFFH are for the bank area.
The addresses of the common area are from D000H to EFFFH, and addresses A000H to CFFFH are for the bank area.
5.3.5. RESET CIRCUIT
The output from pin 1 of the Reset IC (IC3) resets the gate array (IC1).
1. During a power surge, a positive reset pulse of 50 msec or more is generated and the system is reset completely.
This is done to prevent partial resetting and system runaway during a power fluctuation.
2. When pin 1 of IC3 becomes low, it will prohibit the RAM (IC4) from changing data.
The RAM (IC4) will go into the backup mode, when it is backed up by a lithium battery.
3. The watch dog timer, built-in the gate array (IC1), is initialized about every 1.5 ms.
When a watch dog error occurs, pin 113 of the gate array (IC1) becomes low.
The terminal of the WDERR signal is connected to the reset line so the WDERR signal works as the reset signal.
The terminal of the WDERR signal is connected to the reset line so the WDERR signal works as the reset signal.
108
KX-FT78RU-B / KX-FT78RU-W
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