Panasonic BB-HCM581CE Service Manual ▷ View online
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BB-HCM581CE
4.2.
Camera Block (Image signal processing, LENS control)
[CCD Board, VIDEO Board]
• IC701 is a CCD image sensor of approximately 320 thousand pixels, which outputs the image signal (CCD_OUT) of an VGA
(640x480) size.
• IC803: This IC is to remove noise in the CCD_OUT signal, adjust the gain and output the 10-bit data (AFE_D[9:0]).
The pixel clock (PCLK: 12.2727MHz) and CCD_Hdrive signal are output based on the timing of the synchronizing signals
(HD_AFE and VD_AFE) that are generated by the CLOCK signal from the IC804.The synchronizing signals (HD_AFE and
VD_AFE) are output from the CPU (IC102) on the CPU board.
The pixel clock (PCLK) and 10-bit data (AFE_D [9:0]) that are output from the IC803 are entered in the LVDS Transmitter IC
on IC806, and after being parallel-serial converted, they are converted into the two-wire differential signals. Then the signals
are transmitted to the LVDS Receiver IC (IC121) on the CPU board. In the LVDS Receiver IC (IC121), the signals are then
serial-parallel converted to recover the pixel clock and the 10-bit data, which are entered into the CPU (IC102). (Refer to Fig.
1.)
(HD_AFE and VD_AFE) that are generated by the CLOCK signal from the IC804.The synchronizing signals (HD_AFE and
VD_AFE) are output from the CPU (IC102) on the CPU board.
The pixel clock (PCLK) and 10-bit data (AFE_D [9:0]) that are output from the IC803 are entered in the LVDS Transmitter IC
on IC806, and after being parallel-serial converted, they are converted into the two-wire differential signals. Then the signals
are transmitted to the LVDS Receiver IC (IC121) on the CPU board. In the LVDS Receiver IC (IC121), the signals are then
serial-parallel converted to recover the pixel clock and the 10-bit data, which are entered into the CPU (IC102). (Refer to Fig.
1.)
• Frequency of the IC803 clock (CLOCK signal) is 24.5454MHz and the clock signal is generated in the IC804 based on timing of
the crystal oscillator (X801).
• The IC803 is controlled by the serial signals (CS_AFE, SDI, and SCL) in the CPU (IC102).
The SDI and SCL signals in the serial signals are shared and used in the DA converter (IC903) and the motor driver (IC901)
that are mounted on the LENS board. (Refer to Fig. 2.)
that are mounted on the LENS board. (Refer to Fig. 2.)
• Hard reset (RESET) of IC803 is controlled by GPIO of IC102 on the CPU board.
• IC802 receives the V drive timing signals (Vdrive: CH1, CH2, and XV1-XV4) from the IC803, and outputs the IC701 (CCD) drive
• IC802 receives the V drive timing signals (Vdrive: CH1, CH2, and XV1-XV4) from the IC803, and outputs the IC701 (CCD) drive
V drive signal (CCD_Vdrive: V1-V4).
• The power supplies used in the camera unit are generated +15V and -5.5V in the IC801 and +3.3V from the +5.7V power sup-
plied from the TILT board.
The power supplies are generated +15V and -5.5V in the IC801 and +3.3V and -0.4V in the IC809 for driving the CCD.
Figure 1 Video Signal Transmission via LVDS
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BB-HCM581CE
Figure 2 Sharing of Serial Signals (SDI and SCL)
[CPU Board]
• Pixel clock and 10-bit RAW data that are output from the IC803 are transmitted to the LVDS Receiver IC (IC121) on the CPU
board via the LVDS Transmitter. In the LVDS Receiver IC (IC121), they are serial-parallel converted to recover the pixel clock
(CAM_CLK) and 10-bit RAW data (CAMD [11:2]), and the recovered pixel clock and 10-bit RAW data are entered into the CPU
(IC102).
(CAM_CLK) and 10-bit RAW data (CAMD [11:2]), and the recovered pixel clock and 10-bit RAW data are entered into the CPU
(IC102).
• In the VIDEO SIGNAL Processor unit that is imbedded in IC102, the RAW data is subjected to such signal processing as OB
clamping, white balancing, and É¡ processing, then the RAW data is temporary recorded in the external SDRAM. The RAW data
is subjected to the three-step processing that is composed of pixel correction, YC generation and scaling, and the data after the
processing is recorded in the same external SDRAM as the image data.
is subjected to the three-step processing that is composed of pixel correction, YC generation and scaling, and the data after the
processing is recorded in the same external SDRAM as the image data.
• The synchronizing signals (CCDHD and CCDVD) and AFE control serial signals (AFE_LD, SDI, and SCL) from the CPU
(IC102), are sent to the AFE IC (IC803) on the VIDEO board via CN102.
[LENS Board]
Camera has 21 X optical zoom lens. This lens unit has the ZOOM lens drive motor, the FOCUS lens drive motor, the IRIS unit,
and the position detection circuit for ZOOM and FOCUS lens, respectively. These components are controlled from the CPU
(IC102) on the CPU board.
and the position detection circuit for ZOOM and FOCUS lens, respectively. These components are controlled from the CPU
(IC102) on the CPU board.
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BB-HCM581CE
[LENS drive motor control]
The CPU controls the driver (IC901) for the LENS motor drive that is mounted on the LENS board by the three-wire serial sig-
nals (SDI, SCL, and MO_LD) and by the motor drive timing signal (VD_MOT). The output current, pulse period, and the number
of pulses are also set up by the driver. This LENS motor drive driver (IC901) controls both of the ZOOM lens drive and FOCUS
lens drive motors using the micro step drive control method. The power supply to drive the motors is +5.7V that is supplied by
the DC-DC converter circuit on the TILT board via the VIDEO board.
nals (SDI, SCL, and MO_LD) and by the motor drive timing signal (VD_MOT). The output current, pulse period, and the number
of pulses are also set up by the driver. This LENS motor drive driver (IC901) controls both of the ZOOM lens drive and FOCUS
lens drive motors using the micro step drive control method. The power supply to drive the motors is +5.7V that is supplied by
the DC-DC converter circuit on the TILT board via the VIDEO board.
[IRIS drive control]
The IRIS has been adjusted in the factory and the adjusted values are saved in the Flash memory (IC104) on the CPU board. In
the initialization process when the power is turned ON, the adjusted values are written in the DA converter (IC903) on the LENS
board. No subsequent process to write the data into the DA converter will be carried out. Once the adjusted values are written in
the DA converter, the output voltage from the DA converter can be controlled. The DA output is applied in the IRIS control cir-
cuit. The IRIS unit of the lens is controlled with the method called the Pulse Width Modulation (PWM).
the initialization process when the power is turned ON, the adjusted values are written in the DA converter (IC903) on the LENS
board. No subsequent process to write the data into the DA converter will be carried out. Once the adjusted values are written in
the DA converter, the output voltage from the DA converter can be controlled. The DA output is applied in the IRIS control cir-
cuit. The IRIS unit of the lens is controlled with the method called the Pulse Width Modulation (PWM).
[LED control]
Red and green LEDs are used in the LED (LED901) indicator. LEDs are turned on, blinked or turned off by turning ON/OFF the
transistors (Q901 and Q902) that are connected to the LEDs. The transistors are turned ON/OFF from the output port of the
CPU (IC102) on the CPU board.
transistors (Q901 and Q902) that are connected to the LEDs. The transistors are turned ON/OFF from the output port of the
CPU (IC102) on the CPU board.
LED_R
LED_G
Q901
Q902
LED COLOR
H
H
ON
ON
Orange
H
L
ON
OFF
Red
L
H
OFF
ON
Green
L
L
OFF
OFF
OFF the light
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4.3.
Image Compression Block
• Image compression (JPEG/MPEG-4 encode) function, memory control unit (MCU), ETHERNET MAC, and SD card controller
are built into IC102.
• Picture data input from the camera block is captured in SDRAM (1).
• Captured image data is input to the ZOM block, where the scaling of the image size is done, (an image size of 640 x 480, 320 x
• Captured image data is input to the ZOM block, where the scaling of the image size is done, (an image size of 640 x 480, 320 x
240, or 192 x 177 is generated from the one with the size of 1280 x 1024, or an image size of 320 x 240 or 192 x 177 from the
one with the size of 640 x 480), and is stored in SDRAM again (2).
one with the size of 640 x 480), and is stored in SDRAM again (2).
• The scaled image data is input to the JPEG/MPEG-4 encode section of IC102, and the image is compressed. The compressed
image data is stored in SDRAM again (3).
• After CPU processed the compressed image data for a communication protocol, the data is forwarded to the network via ETH-
ERNET MAC and ETHERNET PHY. And the image data of post-compression is processed for a file and is recorded on the SD
card.
card.
• As for the video output, the captured image data is scaled to a size of NTSC or PAL at the ZOM block, and then it is output from
VIDEO OUT and DAC sections as an analog video signal.
• This analog video signal is amplified by the video amplifier (IC109) and output from CN604 on the IO board with the output
impedance of 75Ω.
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