DOWNLOAD LG 55LM960V (CHASSIS:LD23E) Service Manual ↓ Size: 12.41 MB | Pages: 119 in PDF or view online for FREE

Model
55LM960V (CHASSIS:LD23E)
Pages
119
Size
12.41 MB
Type
PDF
Document
Service Manual
Brand
Device
TV / LCD
File
55lm960v-chassis-ld23e.pdf
Date
PREV: LG 55LM860V (CHASSIS:LD23E) Service Manual

LG 55LM960V (CHASSIS:LD23E) Service Manual ▷ View online

THE    SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE    SYMBOL MARK OF THE SCHEMETIC.
R11019
0
IR_Bla
JK11001
KJA-PH-0-0177
IR_Bla
3
DETECT
4
L
5
GND
1
R
D11001
IR_Bla
C11005
22pF
50V
IR_Bla
C11003
22pF
50V
IR_Bla
X11001
8MHz
IR_Bla
IRB_SPI_CK
IRB_SPI_SS
IRB_SPI_MISO
IRB_SPI_MOSI
R11006
22 IR_Bla
R11007
22 IR_Bla
R11008
22
IR_Bla
R11009
22 IR_Bla
P11001
12507WS-04L
IR_Bla
1
2
3
4
5
JP11002
JP11001
IR_B_RESET
+3.3V_IR_Bla
+3.3V_IR_Bla
10uF
10V
C11004
IR_Bla
C11006
0.1uF
16V
OPT
+3.3V_IR_Bla
L11001
BLM18PG121SN1D
IR_Bla
+3.3V_IR_Bla
R11022
4.7K
IR_Bla
+3.3V_NORMAL
+3.3V_IR_Bla
+5V_NORMAL
C11009
0.1uF
16V
OPT
R11021
10K
IR_Bla
Q11003
MMBT3904(NXP)
IR_Bla
E
B
C
R11001
1K
IR_Bla
C11010
0.1uF
16V
IR_Bla
D11002
IR_Bla
IC11002
MC96FR3128R
DEV_IR_Bla
3
XOUT
2
XIN
4
P20/RESETB
1
VSS
6
P11/KS9/MISO1
5
P10/KS8/MOSI1
7
P12/KS10/INT0
8
P13/KS11/INT1
9
P14/KS12/SS1/INT2
10
P15/KS13/XCK1/INT3
11
P16/KS14/MOSI0
12
P17/KS15/MISO0
13
P30/SS0/EC2/EXTREF
14
P31/XCK0/SENSOR
15
P36/INT0/XCK0
16
P37/INT1/SS0
17
P00/KS0/T0
18
P01/KS1/T1/PWM1
19
P02/KS2/T2
20
P03/KS3/T3/PWM3
21
P04/KS4/EC0
22
P05/KS5/EC3
23
P06/KS6
24
P07/KS7
25
P21/INT2/DSCL
26
P22/INT3/DSDA
27
REMOUT
28
VDD
Q11002
AO3438
IR_Bla
G
D
S
R11015
100
IR_Bla
Q11001
SBT2222A_AUK
IR_Bla
E
B
C
R11020
0
IR_Bla
C11008
10uF
IR_Bla
IR Blaster/Boost
LG1152 A1
2011. 06. 02
IR_B Micom Download
IR BLASTER
DSCL
DSDA
94
Close to JK11001
Pattern Width : 0.5mm
Pattern Width : 0.5mm
THE    SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE    SYMBOL MARK OF THE SCHEMETIC.
R154
100
1%
R162
33
RXBCLKP
+3.3V_IO
+3.3V_IO
R166
10K
R125
33
RXA3N
FLASH_WP
RXA2N
I2C_SDA_PQ
C120
0.1uF
+0.9VDC
TDO
C125
0.1uF
16V
C154
10uF
25V
RXA1N
+3.3V
R120
100
1%
RXB2P
R134
0
RXACLKP
C112
0.1uF
P102
12507WR-04L
1
2
3
4
5
I2C_SDA_S
I2C_SDA_PQ
RXA1P
R169
47K
OPT
I2C_SDA_S
R181
33
RXB2N
TCK
R110
100
1%
+0.9VDC
R172
4.7K
R178
0
C148
10uF
25V
XTAL_OUT
R118
100
1%
R152
33
TMS
R130
33
RXB0N
+3.3V
R175
1K
SPI_SCLK
C115
0.1uF
I2C_SCL_PQ
C118
0.1uF
+3.3V
P103
12507WR-04L
1
2
3
4
5
+1.8LVDS_TX
R124
33
SPI_DI
+3.3V
TX5P
RXB4P
SPI_CS
R135
0
C100
27pF
50V
R173
4.7K
+0.9AVDD
TX7P
C114
0.1uF
C122
0.1uF
3.3K
R102
XTAL_IN
R117
100
1%
+3.3V
+1.8V
I2C_SCL_S
R127
33
+1.8LVDS_RX
R105 3.3K
R167
47K
TDI
RXBCLKN
SPI_CS
TDO
TX7N
R115
100
1%
TX0N
+3.3V
RXB3N
TX2N
+0.9AVDD
RXB4N
C116
0.1uF
R155
100
1%
R129
33
R156
33
OPT
C113
0.1uF
XTAL_IN
+0.9VDC
FLASH_WP
C151
10uF
25V
C103
33pF
50V
OPT
C159
0.1uF
16V
R148
33 OPT
C162
0.1uF
16V
R101
10K
C111
0.1uF
+1.8LVDS_RX
C149
0.1uF
16V
SPI_DO
R158
10K
OPT
IC101
MX25L3206EM2I-12G
SPI_FLASH
3
WP#
2
SO/SIO1
4
GND
1
CS#
5
SI/SIO0
6
SCLK
7
HOLD#
8
VCC
R104 3.3K
3D_LR
UART_TX
R128
33
TDI
R133
0
+3.3V_IO
RXA0P
SPI_SCLK
C104
27pF
50V
C109
0.1uF
SPI_DL_MODE
C163
0.1uF
16V
R176
0
OPT
R149
33
UART_TX
SPI_DI
P100
12507WR-10L
1
2
3
4
5
6
7
8
9
10
11
SPI_DO
SPI_DO
C121
0.1uF
R150
33 OPT
R180
33
TX3P
R121
100
1%
TX5N
R131
33
TX_LOCK
C119
0.1uF
+1.8LVDS_RX
+0.9VDC
C107
33pF
50V
OPT
C161
0.1uF
16V
UART_RX
SPI_CS
TX6P
C105
33pF
50V
OPT
TX0P
FLASH_WP
RXA4N
LG1122_RST
+3.3V
R122
100
1%
RXA0N
R163
33 OPT
RXB3P
SPI_DL_MODE
RXB1N
R177
0
OPT
SPI_SCLK
C108
0.1uF
R138
33 OPT
SW100
JTP-1127WEM
1
2
4
3
R153
33
R136
33 OPT
TX1N
+1.8LVDS_TX
RXB1P
RXA4P
UART_RX
R174
3.3K
+0.9AVDD
R159
33
RXB0P
RBF
R179
0
R123
100
1%
R183
33
+1.8LVDS_TX
R103 3.3K
AGP_EN
R160
33
I2C_SCL_PQ
C110
0.1uF
R168
10K
R161
33
TRST_N
3D_EN
TRST_N
R113
10K
P101
12507WR-08L
1
2
3
4
5
6
7
8
9
TCK
R109
100
1%
R114
100
1%
R106
1M
TX4P
RXA2P
SPI_DI
+3.3V
TX4N
+0.9VDC
R157
4.7K
TX3N
R139
0 OPT
TX6N
TX2P
+1.8V
RXACLKN
R132
33
I2C_SCL_S
TX1P
+1.8V
C157
10uF
25V
R182
33
RXA3P
R126
33
C123
0.1uF
C124
0.1uF
R137
33 OPT
+1.8V_AVDD
+1.8LVDS_RX
TMS
R151
33 OPT
XTAL_OUT
C117
0.1uF
R146
33
+0.9V
PWM_BPL
R164
33
R165
33
+3.3V
R112
1K
R111
1K
L102
MLB-201209-0120P-N2
L100
MLB-201209-0120P-N2
L101
MLB-201209-0120P-N2
L103
MLB-201209-0120P-N2
L105
MLB-201209-0120P-N2
C126
4.7uF
10V
C127
4.7uF
10V
C129
4.7uF
10V
C131
4.7uF
10V
C134
4.7uF
10V
C135
4.7uF
10V
C137
4.7uF
10V
C139
4.7uF
10V
C144
4.7uF
10V
C153
4.7uF
10V
+1.8V
C142
4.7uF
10V
C152
4.7uF
10V
L104
MLB-201209-0120P-N2
+1.8V_AVDD
+1.8V_AVDD
C158
0.1uF
16V
R185
10K
OPT
+3.3V
3.3K
R186
OPT
L/DIM0_SCLK
L/DIM0_MOSI
L/DIM0_VS
R107
10K
120Hz
R108
10K
W/O_TCON
+3.3V
R116
10K
W_TCON
R119
10K
240Hz
+3.3V
SOC_OPT
+3.3V
R170
10K
L9(LG1152)
R171
10K
MTK
SOC_OPT
FRAME_OPT
DISPLAY_OPT
REVERSE_OPT
TCON_OPT
TCON_OPT
FRAME_OPT
+3.3V
R189
10K
OLED
R190
10K
LCD
R187
10K
IMAGE_NORMAL
+3.3V
R188
10K
IMAGE_REVERSE
REVERSE_OPT
DISPLAY_OPT
R191
0
IC100
LG1122
RXA0P
AC1
RXA0N
AC2
RXA1P
AB3
RXA1N
AC3
RXA2P
AB2
RXA2N
AB1
RXACLKP
AA1
RXACLKN
AA2
RXA3P
Y3
RXA3N
AA3
RXA4P
Y2
RXA4N
Y1
RXB0P
W1
RXB0N
W2
RXB1P
V3
RXB1N
W3
RXB2P
V2
RXB2N
V1
RXBCLKP
U1
RXBCLKN
U2
RXB3P
T3
RXB3N
U3
RXB4P
T2
RXB4N
T1
L_VSOUT_LD
B26
R_VSOUT_LD
E2
M0_SCLK
C26
M0_MOSI
E22
M1_SCLK
D24
M1_MOSI
G22
M2_SCLK
D2
M2_MOSI
E1
M3_SCLK
D1
M3_MOSI
D3
UART_RXD
G3
UART_TXD
H3
SPI_SCLK
G1
SPI_CS
G2
SPI_DI
F2
SPI_DO
F1
SDA_M
J1
SCL_M
J2
SDA_S
H1
SCL_S
H2
SMODE
K2
TMODE0
J3
TMODE1
K3
TMODE2
L3
TMODE3
M3
TRST_N
M2
TDO
L1
TDI
L2
TCLK
M1
TMS
N1
PORES_N
K1
XTALO
AF6
XTALI
AE6
MON_SYNC0
N2
MON_SYNC1
N3
MON_INTR
P3
VIREF_REXT
C1
TX_LOCKN
C2
GPIO[0]
AB5
GPIO[1]
AB4
GPIO[2]
AD5
GPIO[3]
AC5
GPIO[4]
AE4
GPIO[5]
AD4
GPIO[6]
AC4
GPIO[7]
AF3
GPIO[8]
AE3
GPIO[9]
AD3
GPIO[10]
AF2
GPIO[11]
AE2
GPIO[12]
AD2
GPIO[13]
AE1
GPIO[14]
B25
GPIO[15]
B24
TX0P
B2
TX0N
A2
TX1P
A3
TX1N
B3
TX2P
C4
TX2N
C3
TX3P
B4
TX3N
A4
TX4P
A5
TX4N
B5
TX5P
C6
TX5N
C5
TX6P
B6
TX6N
A6
TX7P
A7
TX7N
B7
TXA0P
A23
TXA0N
B23
TXA1P
C22
TXA1N
C23
TXA2P
B22
TXA2N
A22
TXACLKP
A21
TXACLKN
B21
TXA3P
C20
TXA3N
C21
TXA4P
B20
TXA4N
A20
TXB0P
A19
TXB0N
B19
TXB1P
C18
TXB1N
C19
TXB2P
B18
TXB2N
A18
TXBCLKP
A17
TXBCLKN
B17
TXB3P
C16
TXB3N
C17
TXB4P
B16
TXB4N
A16
TXC0P
A15
TXC0N
B15
TXC1P
C14
TXC1N
C15
TXC2P
B14
TXC2N
A14
TXCCLKP
A13
TXCCLKN
B13
TXC3P
C12
TXC3N
C13
TXC4P
B12
TXC4N
A12
TXD0P
A11
TXD0N
B11
TXD1P
C10
TXD1N
C11
TXD2P
B10
TXD2N
A10
TXDCLKP
A9
TXDCLKN
B9
TXD3P
C8
TXD3N
C9
TXD4P
B8
TXD4N
A8
GPIO[16]
C25
GPIO[17]
C24
GPIO[18]
AD1
GPIO[19]
R1
GPIO[20]
R2
GPIO[21]
R3
GPIO[22]
P1
GPIO[23]
A25
GPIO[24]
D23
GPIO[25]
D22
GPIO[26]
F22
GPIO[27]
E23
GPIO[28]
E3
GPIO[29]
F3
GPIO[30]
A24
GPIO[31]
P2
IC100
LG1122
VSS_1
B1
VSS_2
C7
VSS_3
D4
VSS_4
D5
VSS_5
D6
VSS_6
D7
VSS_7
D8
VSS_8
D18
VSS_9
D19
VSS_10
D20
VSS_11
D21
VSS_12
D25
VSS_13
D26
VSS_14
E4
VSS_15
E5
VSS_16
E6
VSS_17
E7
VSS_18
E8
VSS_19
E9
VSS_20
E10
VSS_21
E11
VSS_22
E12
VSS_23
E13
VSS_24
E14
VSS_25
E15
VSS_26
E16
VSS_27
E17
VSS_28
E18
VSS_29
E19
VSS_30
E21
VSS_31
E24
VSS_32
F5
VSS_33
F7
VSS_34
F8
VSS_35
F9
VSS_36
F10
VSS_37
F11
VSS_38
F12
VSS_39
F13
VSS_40
F14
VSS_41
F15
VSS_42
F16
VSS_43
F17
VSS_44
F18
VSS_45
F19
VSS_46
F21
VSS_47
F23
VSS_48
G5
VSS_49
G21
VSS_50
G23
VSS_51
H5
VSS_52
H8
VSS_53
H9
VSS_54
H10
VSS_55
H11
VSS_56
H12
VSS_57
H13
VSS_58
H14
VSS_59
H15
VSS_60
H16
VSS_61
H17
VSS_62
H18
VSS_63
H19
VSS_64
H21
VSS_65
H22
VSS_66
H23
VSS_67
J5
VSS_68
J8
VSS_69
J19
VSS_70
J21
VSS_71
J22
VSS_72
K4
VSS_73
K5
VSS_74
K8
VSS_75
K10
VSS_76
K11
VSS_77
K12
VSS_78
K13
VSS_79
K14
VSS_80
K15
VSS_81
K16
VSS_82
K17
VSS_83
K19
VSS_84
K21
VSS_85
K22
VSS_86
L4
VSS_87
L5
VSS_88
L8
VSS_89
L10
VSS_90
L11
VSS_91
L12
VSS_92
L13
VSS_93
L14
VSS_94
L15
VSS_95
L16
VSS_96
L17
VSS_97
L19
VSS_98
L21
VSS_99
L22
VSS_100
M4
VSS_101
M5
VSS_102
M6
VSS_103
M8
VSS_104
M10
VSS_105
M11
VSS_106
M12
VSS_107
M13
VSS_108
M14
VSS_109
M15
VSS_110
M16
VSS_111
M17
VSS_112
M19
VSS_113
M21
VSS_114
M22
VSS_115
N4
VSS_116
N5
VSS_117
N6
VSS_118
N8
VSS_119
N10
VSS_120
N11
VSS_121
N12
VSS_122
N13
VSS_123
N14
VSS_124
N15
VSS_125
N16
VSS_126
N17
VSS_127
N19
VSS_128
N21
VSS_129
N22
VSS_130
N24
VSS_131
P4
VSS_132
P5
VSS_133
P6
VSS_134
P8
VSS_135
P10
VSS_136
P11
VSS_137
P12
VSS_138
P13
VSS_139
P14
VSS_140
P15
VSS_141
P16
VSS_142
P17
VSS_143
P19
VSS_144
P21
VSS_145
P22
VSS_146
P24
VSS_147
R4
VSS_148
R5
VSS_149
R6
VSS_150
R8
VSS_151
R10
VSS_152
R11
VSS_153
R12
VSS_154
R13
VSS_155
R14
VSS_156
R15
VSS_157
R16
VSS_158
R17
VSS_159
R19
VSS_160
R21
VSS_161
R22
VSS_162
T5
VSS_163
T6
VSS_164
T8
VSS_165
T10
VSS_166
T11
VSS_167
T12
VSS_168
T13
VSS_169
T14
VSS_170
T15
VSS_171
T16
VSS_172
T17
VSS_173
T19
VSS_174
T21
VSS_175
T22
VSS_176
U5
VSS_177
U6
VSS_178
U8
VSS_179
U10
VSS_180
U11
VSS_181
U12
VSS_182
U13
VSS_183
U14
VSS_184
U15
VSS_185
U16
VSS_186
U17
VSS_187
U19
VSS_188
U21
VSS_189
U22
VSS_190
V5
VSS_191
V6
VSS_192
V8
VSS_193
V19
VSS_194
V21
VSS_195
V22
VSS_196
W5
VSS_197
W6
VSS_198
W8
VSS_199
W9
VSS_200
W10
VSS_201
W11
VSS_202
W12
VSS_203
W13
VSS_204
W14
VSS_205
W15
VSS_206
W16
VSS_207
W17
VSS_208
W18
VSS_209
W19
VSS_210
W21
VSS_211
W22
VSS_212
Y4
VSS_213
Y5
VSS_214
Y21
VSS_215
Y22
VSS_216
AA4
VSS_217
AA7
VSS_218
AA8
VSS_219
AA9
VSS_220
AA10
VSS_221
AA11
VSS_222
AA12
VSS_223
AA13
VSS_224
AA14
VSS_225
AA15
VSS_226
AA16
VSS_227
AA17
VSS_228
AA18
VSS_229
AA19
VSS_230
AA20
VSS_231
AA21
VSS_232
AA22
VSS_233
AA23
VSS_234
AB6
VSS_235
AB7
VSS_236
AB8
VSS_237
AB9
VSS_238
AB10
VSS_239
AB11
VSS_240
AB12
VSS_241
AB13
VSS_242
AB14
VSS_243
AB15
VSS_244
AB16
VSS_245
AB17
VSS_246
AB18
VSS_247
AB19
VSS_248
AB20
VSS_249
AB21
VSS_250
AB22
VSS_251
AB23
VSS_252
AC6
VSS_253
AC7
VSS_254
AC8
VSS_255
AC9
VSS_256
AC10
VSS_257
AC23
VSS_258
AC24
VSS_259
AC25
VSS_260
AC26
VSS_261
AD6
VSS_262
AD7
VSS_263
AD8
VSS_264
AD17
VSS_265
AD18
VSS_266
AE8
VSS_267
AF4
VSS_268
AF8
IC100
LG1122
VDD_1
J9
VDD_2
J10
VDD_3
J11
VDD_4
J16
VDD_5
J17
VDD_6
J18
VDD_7
K9
VDD_8
K18
VDD_9
L9
VDD_10
L18
VDD_11
M9
VDD_12
M18
VDD_13
N9
VDD_14
N18
VDD_15
P9
VDD_16
P18
VDD_17
R9
VDD_18
R18
VDD_19
T9
VDD_20
T18
VDD_21
U9
VDD_22
U18
VDD_23
V9
VDD_24
V10
VDD_25
V11
VDD_26
V12
VDD_27
V13
VDD_28
V14
VDD_29
V15
VDD_30
V16
VDD_31
V17
VDD_32
V18
VDD33_1
F6
VDD33_2
F20
VDD33_3
G6
VDD33_4
H6
VDD33_5
J6
VDD33_6
K6
VDD33_7
L6
VDD33_8
Y6
VDD33_9
AA6
VDD18_1
E20
VDD18_2
F4
VDD18_3
G4
VDD18_4
H4
VDD18_5
J4
VDD18_6
AA5
LVRX_VDD18_1
T4
LVRX_VDD18_2
U4
LVRX_VDD18_3
V4
LVRX_VDD18_4
W4
LVTX_VDD18_1
D9
LVTX_VDD18_2
D10
LVTX_VDD18_3
D11
LVTX_VDD18_4
D12
LVTX_VDD18_5
D13
LVTX_VDD18_6
D14
LVTX_VDD18_7
D15
LVTX_VDD18_8
D16
LVTX_VDD18_9
D17
LVTX_VDD_1
J12
LVTX_VDD_2
J13
LVTX_VDD_3
J14
LVTX_VDD_4
J15
AVDD09_1
AE7
AVDD09_2
AF7
AVDD18_1
AE5
AVDD18_2
AF5
OPT_READY_1
OPT_READY_2
L/DIMMING_OPT
R142
10K
OPT
R144
10K
OPT
R143
10K
R145
10K
+3.3V
+3.3V
R140
10K
L/D_ON_FRC
R141
10K
L/D_ON_MAIN
OPT_READY_2
+3.3V
OPT_READY_1
L/DIMMING_OPT
X100
24.75MHz
4
GND_2
1
X-TAL_1
2
GND_1
3
X-TAL_2
PANEL_CTL
R147
3.3K
FRC-III(LG1122)
1
6
XTAL(24.75MHz)
+3.3V Power Separation
 RESET Input
  1) LG1122_RST  : From Main SOC
  2) HW_RESET    : From  HW Switch
  3) SPI_DL_MODE : Download Mode to Flash Mem
+0.9V Power Separation
SPI/I2C For Aardvak Interface
+0.9VDC Decaps
+3.3V_IO Decaps
SPI FLASH(4MByte)
+0.9AVDD Decaps
+1.8VLVDS_RX Decaps
UART For CPU
The Vx1_HS Tx AC-coupling Caps must be 
placed near by LG1122
+1.8VLVDS_TX Decaps
GPIO[1:0]
 : Local Dimming Debugging 
GPIO[7:3] = PWM[4:0]
 1) GPIO[3] : 120Hz Mode --> 60 or 120Hz (Programmable)
              240Hz Mode --> 120 or 240Hz (Programmable)
 2) GPIO[4] : 120Hz Mode --> 60 or 120Hz (Programmable)
              240Hz Mode --> 120 or 240Hz (Programmable)
 3) GPIO[5] : 120Hz Mode --> 120 or 240Hz (Programmable)
              240Hz Mode --> 240 or 480Hz (Programmable)
 
 4) GPIO[6] : 120Hz Mode --> 120Hz (Fixed)
              240Hz Mode --> 240Hz (Fixed)
 5) GPIO[7] : 120Hz Mode --> 120Hz (Fixed)
              240Hz Mode --> 240Hz (Fixed)
GPIO[8]
 : External Vsync input for Local Dimming block 
 
GPIO[10]
 : T-Con L/R Sync Monitor(AR)
GPIO[12:11]
 : S/W I2C_Master CH
GPIO[26:16]
 : BLU Direct Control CH
GPIO[28:27]
 : I2C for PQ tunning
For JTAG Interface
All of OPT decaps must be placed on PCB Bottom side 
           
Vx1_HS output swing level control
via external resistor
I2C For PQ tunning
I2C Slave Address 
0x1C (Direct access)
0xB2 (In-direct access)
+1.8V Power Separation
240Hz Back-End Board
2011. 07. 05
Write Protection
- HIGH : Normal Operation
- LOW : Write Protection
Will be deleted pull-up resistor from B0+3D Depth B’d
READY FOR H/W OPTION
OPT_READY_1
11
(for 72INCH)
JIG_OPT
240Hz
OPT_READY_2
With_TCON
IMAGE_OPT
OPTION NAME
LOW
20
21
DISPLAY_OPT
OLED
22
IMAGE_NORMAL
L/D_ON_FRC
OPT
L9 (LG1152)
120Hz
13
GPIO NO
15
MTK
OPT
FRAME_OPT
Default
Without_TCON
(for FRC3 JIG)
12
L/D_ON_MAIN
(for NON_72INCH)
IMAGE_OPT
SOC_OPT
Default
14
L/DIMMING_OPT
HIGH
LCD
THE    SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE    SYMBOL MARK OF THE SCHEMETIC.
DDR0_DATA[14]
DDR0_A[0]
DDR0_A[7]
DDR1_A[0]
DDR0_A[6]
DDR0_DATA[12]
DDR1_A[2]
DDR0_DATA[10]
DDR1_DATA[1]
DDR0_DATA[8]
DDR1_DATA[12]
DDR1_DATA[14]
DDR0_A[10]
DDR0_DATA[11]
DDR0_DATA[4]
DDR0_A[5]
DDR1_A[4]
DDR1_A[6]
DDR1_DATA[13]
DDR0_DATA[0]
DDR1_A[4]
DDR1_A[6]
DDR0_DATA[12]
DDR0_DATA[7]
DDR1_A[2]
DDR0_A[3]
DDR1_DATA[6]
DDR1_A[0]
DDR1_A[10]
DDR1_DATA[0]
DDR0_A[10]
DDR1_A[12]
DDR1_DATA[8]
DDR0_A[9]
DDR0_DATA[5]
DDR1_A[7]
DDR0_A[8]
DDR1_DATA[14]
DDR1_DATA[7]
DDR0_DATA[4]
DDR0_A[5]
DDR0_DATA[5]
DDR0_A[11]
DDR0_DATA[2]
DDR1_A[8]
DDR0_A[12]
DDR0_A[7]
DDR0_A[9]
DDR1_DATA[6]
DDR0_A[11]
DDR1_A[3]
DDR1_DATA[10]
DDR1_DATA[10]
DDR1_DATA[8]
DDR1_DATA[7]
DDR1_DATA[11]
DDR0_DATA[9]
DDR1_DATA[4]
DDR0_A[1]
DDR0_A[3]
DDR1_DATA[13]
DDR0_A[2]
DDR1_DATA[3]
DDR1_A[8]
DDR0_A[4]
DDR1_A[1]
DDR1_A[1]
DDR1_A[9]
DDR1_A[5]
DDR0_A[2]
DDR0_DATA[1]
DDR1_DATA[4]
DDR0_A[8]
DDR0_A[12]
DDR1_DATA[3]
DDR0_DATA[15]
DDR1_A[12]
DDR1_DATA[15]
DDR0_DATA[10]
DDR1_A[11]
DDR0_DATA[2]
DDR1_DATA[12]
DDR1_DATA[9]
DDR0_DATA[0]
DDR0_A[0]
DDR0_DATA[6]
DDR0_A[4]
DDR1_A[11]
DDR0_DATA[9]
DDR1_A[3]
DDR0_DATA[1]
DDR0_A[6]
DDR1_DATA[9]
DDR0_DATA[8]
DDR1_DATA[15]
DDR1_A[7]
DDR1_DATA[2]
DDR0_DATA[6]
DDR0_DATA[15]
DDR1_A[9]
DDR1_DATA[0]
DDR0_DATA[7]
DDR1_DATA[2]
DDR0_A[1]
DDR0_DATA[11]
DDR1_DATA[5]
DDR1_A[5]
DDR0_DATA[14]
DDR1_DATA[11]
DDR0_DATA[13]
DDR0_DATA[3]
DDR0_DATA[3]
DDR1_A[10]
DDR0_DATA[13]
DDR1_DATA[5]
DDR1_DATA[1]
DDR0_BA[2]
DDR1_CKE
R222
100 1%
C237
0.1uF
DDR0_BA[0]
DDR1_DM[1]
R210
1K
1%
R216
240
1%
DDR0_RASN
DDR1_RASN
DDR0_WEN
C238
0.1uF
DDR0_A[0-12]
DDR1_DM[0]
DDR0_BA[1]
DDR0_RESET_N
+1.5V
C224
0.1uF
R207
1K
1%
+0.75V_VREF1_D0
C241
0.1uF
DDR1_DQS_N[1]
+1.5VQ1
DDR1_DATA[0-15]
R219
1K
1%
+0.75V_VREF1_M0
DDR1_A[0-12]
DDR1_BA[0]
+0.75V_VREF0_D1
DDR1_BA[1]
C203
0.1uF
C229
0.1uF
C232
0.1uF
DDR1_RESET_N
C217
0.1uF
R209
1K
1%
+1.5VQ0
DDR1_DQS_N[0]
DDR0_BA[1]
DDR0_BA[0]
+1.5VQ0
DDR1_DQS[1]
C226
0.1uF
C236
0.1uF
DDR1_CASN
R205
1K
1%
C227
1000pF
DDR1_CASN
C209
0.1uF
DDR0_CLK
DDR1_DQS[0]
+0.75V_VREF1_D1
DDR1_A[0-12]
DDR1_DATA[0-15]
DDR0_DATA[0-15]
+1.5VQ0
C228
0.1uF
C230
1000pF
DDR0_CLKN
DDR1_WEN
C202
0.1uF
+0.75V_VREF0_D0
R217
1K
1%
C225
1000pF
DDR1_ODT
C223
0.1uF
C221
1000pF
+1.5VQ1
DDR1_BA[2]
DDR0_CKE
C201
0.1uF
R223
240
1%
DDR0_CLKN
DDR0_CLK
DDR1_RASN
DDR1_ODT
+1.5VQ0
+0.75V_VREF0_D0
R203
1K
1%
+1.5VQ1
DDR0_DATA[0-15]
R211
240
1%
+0.75V_VREF1_D1
DDR1_DQS_N[1]
+0.75V_VREF1_D0
C220
0.1uF
DDR1_CLK
C210
0.1uF
DDR0_DQS_N[1]
+1.5VQ0
DDR0_DM[0]
+1.5VQ1
DDR1_BA[2]
+1.5V
DDR0_ODT
DDR1_CKE
+1.5VQ1
+1.5VQ0
R204
1K
1%
DDR0_DQS[0]
DDR0_CASN
DDR1_BA[0]
DDR0_DQS[0]
DDR0_RASN
+0.75V_VREF0_D1
R208
1K
1%
C212
0.1uF
+0.75V_VREF1_M0
DDR1_CLKN
C218
1000pF
R202
240
1%
C216
0.1uF
DDR0_DQS_N[0]
DDR0_DQS_N[0]
C204
0.1uF
DDR1_CLKN
DDR0_DQS[1]
R214
1K
1%
C206
0.1uF
+0.75V_VREF1_D1
+1.5VQ0
C215
1000pF
C214
0.1uF
+0.75V_VREF1_M1
DDR0_DM[0]
+1.5VQ1
R212
1K
1%
+1.5VQ0
DDR1_DM[0]
R206
1K
1%
DDR0_RESET_N
DDR0_DQS[1]
+0.75V_VREF0_M0
+0.75V_VREF0_M0
C233
1000pF
C242
0.1uF
DDR0_CKE
C213
1000pF
+0.75V_VREF1_M1
DDR0_A[0-12]
+1.5VQ1
DDR1_DQS[0]
DDR1_WEN
DDR1_RESET_N
+0.75V_VREF0_D1
R218
1K
1%
R215
1K
1%
C244
0.1uF
R201
100 1%
DDR0_BA[2]
DDR0_DM[1]
+0.75V_VREF1_D0
+0.75V_VREF0_M1
C211
0.1uF
C235
0.1uF
DDR0_DQS_N[1]
DDR0_DM[1]
R220
1K
1%
DDR1_DQS[1]
DDR1_DM[1]
DDR0_ODT
DDR1_DQS_N[0]
+1.5VQ1
DDR1_CLK
R213
1K
1%
+0.75V_VREF0_M1
H5TQ1G63DFR-PBC
IC200
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
A15
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
NC_6
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
DDR0_CASN
+0.75V_VREF0_D0
DDR0_WEN
DDR1_BA[1]
+1.5VQ1
H5TQ1G63DFR-PBC
IC201
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
A15
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
NC_6
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
+1.5VQ0
L200
MLB-201209-0120P-N2
L201
MLB-201209-0120P-N2
C219
4.7uF
10V
C222
4.7uF
10V
C231
4.7uF
10V
C234
4.7uF
10V
IC100
LG1122
DDR0_A[0]
AB25
DDR0_A[1]
F26
DDR0_A[2]
AB24
DDR0_A[3]
Y24
DDR0_A[4]
G26
DDR0_A[5]
Y25
DDR0_A[6]
G25
DDR0_A[7]
Y26
DDR0_A[8]
G24
DDR0_A[9]
AA26
DDR0_A[10]
H26
DDR0_A[11]
F25
DDR0_A[12]
H24
DDR0_A[13]
AA25
DDR0_A[14]
F24
DDR0_DQ[0]
T26
DDR0_DQ[1]
L24
DDR0_DQ[2]
U24
DDR0_DQ[3]
K26
DDR0_DQ[4]
U26
DDR0_DQ[5]
K24
DDR0_DQ[6]
U25
DDR0_DQ[7]
K25
DDR0_DQ[8]
M25
DDR0_DQ[9]
R26
DDR0_DQ[10]
L26
DDR0_DQ[11]
T24
DDR0_DQ[12]
M26
DDR0_DQ[13]
R25
DDR0_DQ[14]
M24
DDR0_DQ[15]
R24
DDR0_CK
J26
DDR0_CK_N
J25
DDR0_DQS[0]
P26
DDR0_DQS_N[0]
P25
DDR0_DQS[1]
N26
DDR0_DQS_N[1]
N25
DDR0_CKE
J24
DDR0_WE_N
W24
DDR0_RAS_N
V24
DDR0_CAS_N
V25
DDR0_ODT
V26
DDR0_DM[0]
L25
DDR0_DM[1]
T25
DDR0_BA[0]
W25
DDR0_BA[1]
H25
DDR0_BA[2]
W26
DDR0_RST_N
AA24
DDR0_ZQ_CAL
E25
DDR0_VREF0
AB26
DDR0_VREF1
E26
DDR0_VDDQ_1
J23
DDR0_VDDQ_2
K23
DDR0_VDDQ_3
L23
DDR0_VDDQ_4
M23
DDR0_VDDQ_5
N23
DDR0_VDDQ_6
P23
DDR0_VDDQ_7
R23
DDR0_VDDQ_8
T23
DDR0_VDDQ_9
U23
DDR0_VDDQ_10
V23
DDR0_VDDQ_11
W23
DDR0_VDDQ_12
Y23
DDR1_A[0]
AE9
DDR1_A[1]
AF25
DDR1_A[2]
AD9
DDR1_A[3]
AD11
DDR1_A[4]
AF24
DDR1_A[5]
AE11
DDR1_A[6]
AE24
DDR1_A[7]
AF11
DDR1_A[8]
AD24
DDR1_A[9]
AF10
DDR1_A[10]
AF23
DDR1_A[11]
AE25
DDR1_A[12]
AD23
DDR1_A[13]
AE10
DDR1_A[14]
AD25
DDR1_DQ[0]
AF15
DDR1_DQ[1]
AD20
DDR1_DQ[2]
AD14
DDR1_DQ[3]
AF21
DDR1_DQ[4]
AF14
DDR1_DQ[5]
AD21
DDR1_DQ[6]
AE14
DDR1_DQ[7]
AE21
DDR1_DQ[8]
AE19
DDR1_DQ[9]
AF16
DDR1_DQ[10]
AF20
DDR1_DQ[11]
AD15
DDR1_DQ[12]
AF19
DDR1_DQ[13]
AE16
DDR1_DQ[14]
AD19
DDR1_DQ[15]
AD16
DDR1_CK
AF22
DDR1_CK_N
AE22
DDR1_DQS[0]
AF17
DDR1_DQS_N[0]
AE17
DDR1_DQS[1]
AF18
DDR1_DQS_N[1]
AE18
DDR1_CKE
AD22
DDR1_WE_N
AD12
DDR1_RAS_N
AD13
DDR1_CAS_N
AE13
DDR1_ODT
AF13
DDR1_DM[0]
AE20
DDR1_DM[1]
AE15
DDR1_BA[0]
AE12
DDR1_BA[1]
AE23
DDR1_BA[2]
AF12
DDR1_RST_N
AD10
DDR1_ZQ_CAL
AD26
DDR1_VREF0
AF9
DDR1_VREF1
AE26
DDR1_VDDQ_1
AC11
DDR1_VDDQ_2
AC12
DDR1_VDDQ_3
AC13
DDR1_VDDQ_4
AC14
DDR1_VDDQ_5
AC15
DDR1_VDDQ_6
AC16
DDR1_VDDQ_7
AC17
DDR1_VDDQ_8
AC18
DDR1_VDDQ_9
AC19
DDR1_VDDQ_10
AC20
DDR1_VDDQ_11
AC21
DDR1_VDDQ_12
AC22
R221
150
R200
150
LG1122_DDR3
2
6
DDR3 1.5V beCaps - Place these caps near Memory
DDR1 PHY VREF
DDR0 PHY VREF
DDR3 1.5V Decaps - Place these caps near Memory
DDR3 1.5V/0.75V Decap 
- Place these caps near IC100
DDR3 1.5V/0.75V Decap 
- Place these caps near IC100
240Hz Back-End Board
2011. 07. 05
THERMAL
THERMAL
THERMAL
THERMAL
THE    SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE    SYMBOL MARK OF THE SCHEMETIC.
+1.5V
10K
R311
0.1uF
16V
C307
C333
22uF
10V
OPT
C310
10uF
25V
OPT
C318
22pF
50V
C315
22uF
10V
C331
22uF
10V
+1.8V
C314
22uF
10V
+3.3V
0.1uF
16V
C308
R301
22K
1%
C319
1uF
25V
+1.8V
C309
10uF
25V
OPT
C316
22uF
10V
C300
22pF
50V
R303
22K
1%
C306
0.1uF 16V
C327
10uF
25V
OPT
C326
10uF
25V
C323
0.1uF 16V
C313
10uF
25V
0.1uF
16V
C325
IC301
TPS54327DDAR
3
VREG5
2
VFB
4
SS
1
EN
5
GND
6
SW
7
VBST
8
VIN
9
[EP]GND
C311
10uF
25V
C312
22uF
10V
IC303
TPS54327DDAR
3
VREG5
2
VFB
4
SS
1
EN
5
GND
6
SW
7
VBST
8
VIN
9
[EP]GND
10K
R304
C305
0.1uF 16V
C330
10uF
25V
C321
0.01uF
50V
VLCD_POWER
(+12V)
C302
1uF
25V
+3.3V
VLCD_POWER
(+12V)
+1.5V
10K
R305
IC300
TPS54327DDAR
3
VREG5
2
VFB
4
SS
1
EN
5
GND
6
SW
7
VBST
8
VIN
9
[EP]GND
+3.3V
C328
10uF
25V
OPT
VLCD_POWER
(+12V)
C301
1uF
25V
VLCD_POWER
(+12V)
L302
MLB-201209-0120P-N2
L306
MLB-201209-0120P-N2
L307
MLB-201209-0120P-N2
L303
MLB-201209-0120P-N2
C303
3300pF
50V
C335
100pF
50V
IC302
AOZ1038PI
3
AGND
2
VIN
4
FB
1
PGND
5
COMP
6
EN
7
NC_1
8
NC_2
9
[EP]LX
10K
R310
+3.3V
C332
22uF
10V
C329
22uF
10V
+0.9V
R312
3.3K
C320
4700pF
50V
C336
3300pF
50V
OPT
C334
100pF
50V
OPT
+0.9V
0.1uF
16V
C322
C304
0.01uF
50V
R316
0
R308
68K
1%
R315
5.1K
1%
R314
3.6K
1%
R302
18K
1%
R309
22K
1%
R307
22K
1%
R313
0
R300
30K
1%
L305
3.6uH
NR8040T3R6N
L301
3.6uH
NR8040T3R6N
L300
3.6uH
NR8040T3R6N
L304
3.6uH
NR8040T3R6N
R306
4.7K
1%
POWER
3
6
Analog I/O Power  +1.8V
Digital I/O Power   +3.3V
DDR3PHY Power   +1.5V
Core Power    +0.9V
LG1122(FRC-III) Power up Sequence
FRC-III I/O for 3.3V
R2
tss(ms)=[C303(nF)*Vref]/Iss(uA)
R2
R2
R1
FRC-III AIP for 1.8V
Vout=0.765*(1+R1/R2)
Vout=0.765*(1+R1/R2)
R1
R1
Vout=0.765*(1+R1/R2)
FRC-III CORE for 0.9V
FRC-III DDR3 for 1.5V
tss(ms)=[C304(nF)*Vref]/Iss(uA)
tss(ms)=[C321(nF)*Vref]/Iss(uA)
MAX 0.345A
TYP 0.278A
MAX 1.184A
TYP 1.149A
TYP 0.043A
MAX 0.046A
TYP 2.521A
Ton_DIO 20us(min) 
Ton_DDR 40us(min) 
Ton_CORE 40us(min) 
MAX 3.124A
Vout=0.8*(1+R1/R2)
R2
R1
2011. 07. 05
120Hz Back-End Board
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