LG 55EM970V-ZA (CHASSIS:ED23E) Service Manual ▷ View online
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
+3.3V_FPGA
+3.3V_FPGA
+2.5V_FPGA
+2.5V_FPGA
R4061
100
I2C_BE_SCL1
I2C_SCL2
I2C_SDA2
I2C_BE_SDA1
R4001
3.3K
OPT
R4002
3.3K
OPT
R4003
0
R4019
0
R4062
0
R4014
0
M_RFModule_ISP
R4011
22
R4009
0
R4017
0
RXB3P
RXB0P
RXB4P
RXB1N
RXB2N
RXB2P
RXBCLKN
RXB3N
RXBCLKP
RXB0N
RXB1P
RXB4N
RXA3N
RXA1N
RXA3P
RXA0P
RXA2N
RXA1P
RXA2P
RXACLKN
RXA0N
RXACLKP
BACK_CHANNEL_LINK_READY
R4023
0
R4016
0
FPGA_LINK1B_RXOUT4_N
FPGA_LINK1B_RXOUT4_P
FPGA_LINK1B_RXOUT3_N
FPGA_LINK1B_RXOUT3_P
FPGA_LINK1B_RXOUT2_N
FPGA_LINK1B_RXOUT2_P
FPGA_LINK1B_RXOUT1_N
FPGA_LINK1B_RXOUT1_P
FPGA_LINK1B_RXOUT0_N
FPGA_LINK1B_RXOUT0_P
FPGA_LINK1B_RXCLKOUT_N
FPGA_LINK1B_RXCLKOUT_P
AMP_RESET_N
AMP_MUTE
AUD_SCK
R4021
0
AUD_LRCK
AUD_LRCH
R4020
0
AUD_MASTER_CLK
M_RFModule_RESET
IR
R4012
0
FPGA_LINK3B_SMB_CS
FPGA_LINK4B_SMB_CS
FPGA_B_SCK
EXT_COMPENSATION_DONE
EL_VDD_ON_20V
R4022
0
R4015
0
R4018
0
R4005
0
R4013
0
R4004
0
R4010
0
R4024
0
FPGA_LINK1B_SMB_CS
FPGA_LINK2B_SMB_CS
FPGA_LINK5B_SMB_CS
VCXO2_CLK_Y
RXA4N
RXA4P
FPGA_B_SDA
R4025
0
R4026
3.3K
R4027
3.3K
R4008
0
R4007
0
+3.5V_ST
+3.5V_ST
M_REMOTE_RX
M_REMOTE_TX
3D_SYNC_RF
OPTIC_SERDES_RESET
R4029
0
OPT
FPGA_LVDS_INFO
R4030
0
OPTIC_GPIO1
LG1122_RST
FLASH_WP
OPTIC_GPIO1
C4003
0.47uF
16V
C4004
0.47uF
16V
C4005
0.47uF
16V
0.47uF
16V
C4008
0.47uF
16V
C4009
0.47uF
16V
C4010
0.47uF
16V
0.47uF
16V
R4063
1K
R4064
1K
R4033
1K
C4002
4.7uF
10V
C4007
4.7uF
10V
C4001
10uF
25V
C4006
10uF
25V
BACK_CHANNEL_LINK_READY
20V_DET_FPGA
R4035
0
IC2001
XC6SLX16-3CSG324I
IO_L44N_A2_M1DQ7_1
J18
IO_L45N_A0_M1LDQSN_1
K18
IO_L45P_A1_M1LDQS_1
K17
IO_L41N_GCLK8_M1CASN_1
K16
IO_L44P_A3_M1DQ6_1
J16
IO_L42P_GCLK7_M1UDM_1
L15
IO_L41P_GCLK9_IRDY1_M1RASN_1
K15
IO_L36N_A8_M1BA1_1
H14
IO_L29P_A23_M1A13_1
C17
IO_L29N_A22_M1A14_1
C18
IO_L31P_A19_M1CKE_1
D17
IO_L31N_A18_M1A12_1
D18
IO_L33P_A15_M1A10_1
E16
IO_L33N_A14_M1A4_1
E18
IO_L35N_A10_M1A2_1
F18
IO_L35P_A11_M1A7_1
F17
IO_L1N_A24_VREF_1
F16
IO_L1P_A25_1
F15
IO_L38N_A4_M1CLKN_1
G18
IO_L38P_A5_M1CLK_1
G16
IO_L43N_GCLK4_M1DQ5_1
H18
IO_L43P_GCLK5_M1DQ4_1
H17
IO_L37N_A6_M1A1_1
H16
IO_L37P_A7_M1A0_1
H15
IO_L49N_M1DQ11_1
P18
IO_L49P_M1DQ10_1
P17
IO_L51P_M1DQ12_1
T17
IO_L52P_M1DQ14_1
U17
IO_L48N_M1DQ9_1
N18
IO_L48P_HDC_M1DQ8_1
N17
IO_L50N_M1UDQSN_1
N16
IO_L74P_AWAKE_1
P15
IO_L74N_DOUT_BUSY_1
P16
IO_L47N_LDC_M1DQ1_1
M18
IO_L47P_FWE_B_M1DQ0_1
M16
IO_L50P_M1UDQS_1
N15
IO_L53N_VREF_1
N14
IO_L46N_FOE_B_M1DQ3_1
L18
IO_L46P_FCS_B_M1DQ2_1
L17
IO_L42N_GCLK6_TRDY1_M1LDM_1
L16
IO_L51N_M1DQ13_1
T18
IO_L52N_M1DQ15_1
U18
IO_L30P_A21_M1RESET_1
F14
IO_L30N_A20_M1A11_1
G14
IO_L32P_A17_M1A8_1
H12
IO_L32N_A16_M1A9_1
G13
IO_L34P_A13_M1WE_1
K12
IO_L34N_A12_M1BA2_1
K13
IO_L36P_A9_M1BA0_1
H13
IO_L39P_M1A3_1
J13
IO_L39N_M1ODT_1
K14
IO_L40P_GCLK11_M1A5_1
L12
IO_L40N_GCLK10_M1A6_1
L13
IO_L53P_1
M14
IO_L61P_1
L14
IO_L61N_1
M13
VCCO_1_1
E17
VCCO_1_2
G15
VCCO_1_3
J14
VCCO_1_4
J17
VCCO_1_5
M15
VCCO_1_6
R17
IC2001
XC6SLX16-3CSG324I
IO_L33N_0
A8
IO_L39N_0
A11
IO_L41N_0
A12
IO_L37N_GCLK12_0
A10
IO_L35N_GCLK16_0
A9
IO_L62N_VREF_0
A14
IO_L64N_SCP4_0
A15
IO_L66N_SCP0_0
A16
IO_L4N_0
A3
IO_L6N_0
A5
IO_L8N_VREF_0
A6
IO_L5N_0
A4
IO_L10N_0
A7
IO_L1P_HSWAPEN_0
D4
IO_L1N_VREF_0
C4
IO_L2P_0
B2
IO_L2N_0
A2
IO_L3P_0
D6
IO_L3N_0
C6
IO_L4P_0
B3
IO_L5P_0
B4
IO_L6P_0
C5
IO_L10P_0
C7
IO_L8P_0
B6
IO_L11P_0
D8
IO_L11N_0
C8
IO_L33P_0
B8
IO_L34P_GCLK19_0
D9
IO_L34N_GCLK18_0
C9
IO_L35P_GCLK17_0
B9
IO_L36P_GCLK15_0
D11
IO_L36N_GCLK14_0
C11
IO_L37P_GCLK13_0
C10
IO_L38P_0
G9
IO_L38N_VREF_0
F9
IO_L39P_0
B11
IO_L41P_0
B12
IO_L62P_0
B14
IO_L63P_SCP7_0
F13
IO_L63N_SCP6_0
E13
IO_L64P_SCP5_0
C15
IO_L65P_SCP3_0
D14
IO_L65N_SCP2_0
C14
IO_L66P_SCP1_0
B16
VCCO_0_2
B10
VCCO_0_3
B15
VCCO_0_1
B5
VCCO_0_5
D13
VCCO_0_4
D7
VCCO_0_6
E10
Decouplingcapacitors forVCCO Bank1
Decouplingcapacitors forVCCO Bank0
MICOM
-FRC & AMP & T-con
From FPGA to URSA
From DES IC to FPGA
Place Close to IC2001
THERMAL
THERMAL
THERMAL
THERMAL
THERMAL
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
+3.3V_SERDES
C5016
0.1uF
C5017
0.1uF
+2.5V_SERDES
C5020
0.1uF
+2.5V_SERDES
C5006
0.1uF
FPGA_B_SCK
FPGA_B_SDA
C5024
0.1uF
C5004
0.1uF
+2.5V_SERDES
C5002
0.1uF
R5013
10K
R5008
0
R5003
10K
OPT
R5006
2.2K
+3.3V_SERDES
FPGA_B_SCK
FPGA_B_SDA
R5018
2.2K
R5017
2.2K
C5021
5pF
50V
5pF
50V
C5022
5pF
50V
5pF
50V
+3.3V_SERDES
C5003
0.1uF
R5001
10K
OPT
C5005
0.1uF
FPGA_B_SCK
C5015
0.1uF
R5005
2.2K
C5023
0.1uF
+2.5V_SERDES
FPGA_B_SDA
C5019
0.1uF
R5007
0
R5014
10K
+2.5V_SERDES
C5001
0.1uF
C5018
0.1uF
R5012 0
R5009
0
+3.3V_SERDES
C5013
0.033uF
+3.3V_SERDES
C5014
0.033uF
R5019
0
C5008
0.1uF
R5011
0
R5010
0
C5007
0.1uF
OPTIC_SERDES_RESET
OPTIC_SERDES_RESET
L5004
L5005
+3.3V_NORMAL
+3.3V_SERDES
+2.5V_NORMAL
+2.5V_SERDES
FPGA_LINK3B_RXOUT1_P
FPGA_LINK3B_RXOUT0_P
FPGA_LINK3B_RXCLKOUT_N
FPGA_LINK3B_RXOUT4_N
FPGA_LINK3B_RXOUT2_N
FPGA_LINK3B_RXOUT1_N
FPGA_LINK3B_RXOUT2_P
FPGA_LINK3B_RXCLKOUT_P
FPGA_LINK3B_RXOUT3_N
FPGA_LINK3B_RXOUT4_P
FPGA_LINK3B_RXOUT0_N
FPGA_LINK3B_RXOUT3_P
FPGA_LINK4B_RXCLKOUT_P
FPGA_LINK4B_RXCLKOUT_N
FPGA_LINK4B_RXOUT0_P
FPGA_LINK4B_RXOUT0_N
FPGA_LINK4B_RXOUT1_P
FPGA_LINK4B_RXOUT1_N
FPGA_LINK4B_RXOUT2_P
FPGA_LINK4B_RXOUT2_N
FPGA_LINK4B_RXOUT3_P
FPGA_LINK4B_RXOUT3_N
FPGA_LINK4B_RXOUT4_P
FPGA_LINK4B_RXOUT4_N
LINK3B_RXIN_N
LINK3B_RXIN_P
LINK4B_RXIN_N
LINK4B_RXIN_P
R5004
10K
R5002
10K
+3.3V_SERDES
+3.3V_SERDES
R5020
0
+3.3V_SERDES
+2.5V_SERDES
+3.3V_SERDES
R5015
0 OPT
R5016
0
OPT
R5027
10K
OPT
LINK5B_RXIN_N
R5039
0
LINK5B_RXIN_P
+3.3V_SERDES
C5055
0.1uF
+2.5V_SERDES
FPGA_LINK5B_RXOUT4_N
+3.3V_SERDES
+2.5V_SERDES
C5037
0.1uF
FPGA_LINK5B_RXOUT4_P
R5031
2.2K
FPGA_LINK5B_RXOUT3_N
FPGA_LINK5B_RXOUT3_P
R5043
0 OPT
OPTIC_SERDES_RESET
C5059
0.1uF
C5038
0.1uF
FPGA_LINK5B_RXOUT2_N
C5052
0.1uF
R5042
10K
FPGA_LINK5B_RXOUT2_P
FPGA_LINK5B_RXOUT1_N
R5038
0
R5028
10K
C5044
0.1uF
FPGA_LINK5B_RXOUT1_P
+3.3V_SERDES
FPGA_LINK5B_RXOUT0_N
R5046
0
+3.3V_SERDES
FPGA_LINK5B_RXOUT0_P
C5056
0.1uF
R5035
0
C5042
0.1uF
FPGA_LINK5B_RXCLKOUT_N
FPGA_LINK5B_RXCLKOUT_P
+2.5V_SERDES
C5051
0.033uF
FPGA_B_SDA
FPGA_B_SCK
+3.3V_SERDES
FPGA_LINK2B_RXOUT2_N
R5030
10K
+2.5V_SERDES
+2.5V_SERDES
+3.3V_SERDES
C5057
0.1uF
FPGA_LINK2B_RXOUT4_N
R5040
0
R5044
10K
C5039
0.1uF
FPGA_LINK2B_RXOUT0_P
FPGA_LINK2B_RXCLKOUT_P
FPGA_LINK2B_RXOUT4_P
+2.5V_SERDES
FPGA_B_SDA
FPGA_LINK2B_RXOUT1_P
C5053
0.033uF
C5054
0.1uF
R5041
0
R5032
2.2K
R5036
0
LINK2B_RXIN_N
FPGA_LINK2B_RXOUT3_P
C5061
0.1uF
R5029
10K
OPT
FPGA_B_SCK
+3.3V_SERDES
FPGA_LINK2B_RXOUT0_N
C5040
0.1uF
FPGA_LINK2B_RXCLKOUT_N
C5045
0.1uF
FPGA_LINK2B_RXOUT1_N
C5058
0.1uF
LINK2B_RXIN_P
FPGA_LINK2B_RXOUT2_P
R5047
0
FPGA_LINK2B_RXOUT3_N
C5046
0.1uF
OPTIC_SERDES_RESET
R5045
0 OPT
+3.3V_SERDES
R5022
10K
C5030
0.1uF
+2.5V_SERDES
C5028
0.1uF
FPGA_LINK1B_RXOUT3_P
R5025
0
+3.3V_SERDES
FPGA_LINK1B_RXCLKOUT_P
R5026
0
FPGA_B_SDA
FPGA_LINK1B_RXOUT2_N
+3.3V_SERDES
FPGA_LINK1B_RXOUT0_N
FPGA_LINK1B_RXOUT3_N
C5034
0.1uF
FPGA_LINK1B_RXOUT1_N
FPGA_LINK1B_RXOUT4_N
LINK1B_RXIN_P
LINK1B_RXIN_N
+3.3V_SERDES
+3.3V_SERDES
FPGA_LINK1B_RXOUT0_P
R5034
0 OPT
+2.5V_SERDES
C5033
0.033uF
C5029
0.1uF
R5037
0
C5035
0.1uF
R5021
10K
OPT
C5036
0.1uF
R5024
0
C5027
0.1uF
+2.5V_SERDES
C5041
0.1uF
FPGA_LINK1B_RXOUT4_P
FPGA_LINK1B_RXOUT1_P
OPTIC_SERDES_RESET
R5033
10K
FPGA_LINK1B_RXCLKOUT_N
FPGA_LINK1B_RXOUT2_P
R5023
2.2K
FPGA_B_SCK
FPGA_LINK5B_SMB_CS
FPGA_LINK2B_SMB_CS
FPGA_LINK4B_SMB_CS
FPGA_LINK3B_SMB_CS
FPGA_LINK1B_SMB_CS
LINK3B_LOCK_N
LINK4B_LOCK_N
LINK2B_LOCK_N
LINK5B_LOCK_N
LINK1B_LOCK_N
C5026
22uF
10V
22uF
10V
C5025
22uF
10V
22uF
10V
C5062
22uF
10V
22uF
10V
C5060
22uF
10V
22uF
10V
C5043
22uF
10V
22uF
10V
C5066
10uF
25V
10uF
25V
C5065
0.1uF
16V
0.1uF
16V
C5064
10uF
25V
10uF
25V
C5063
0.1uF
16V
0.1uF
16V
IC5002
DS32EL0124
1
VDD33_1
2
NC_1
3
GPIO0
4
GPIO1
5
DC_B
6
RS
7
VDD25_1
8
NC_2
9
NC_3
10
NC_4
11
GPIO2
12
NC_5
13
NC_6
14
NC_7
15
VDD33_2
16
RXIN0+
17
RXIN0-
18
VDD33_3
19
NC_8
20
NC_9
21
NC_10
22
NC_11
23
NC_12
24
NC_13
25
VDD25_2
26
LF_REF
27
LF_CP
28
VDDPLL
29
NC_14
30
RESET
31
LOCK
32
SDA
33
SCK
34
SMB_CS
35
VDD25_3
36
VDD33_4
37
RXCLKOUT+
38
RXCLKOUT-
39
RXOUT0+
40
RXOUT0-
41
RXOUT1+
42
RXOUT1-
43
RXOUT2+
44
RXOUT2-
45
RXOUT3+
46
RXOUT3-
47
RXOUT4+
48
RXOUT4-
49
[EP]GND
IC5004
DS32EL0124
1
VDD33_1
2
NC_1
3
GPIO0
4
GPIO1
5
DC_B
6
RS
7
VDD25_1
8
NC_2
9
NC_3
10
NC_4
11
GPIO2
12
NC_5
13
NC_6
14
NC_7
15
VDD33_2
16
RXIN0+
17
RXIN0-
18
VDD33_3
19
NC_8
20
NC_9
21
NC_10
22
NC_11
23
NC_12
24
NC_13
25
VDD25_2
26
LF_REF
27
LF_CP
28
VDDPLL
29
NC_14
30
RESET
31
LOCK
32
SDA
33
SCK
34
SMB_CS
35
VDD25_3
36
VDD33_4
37
RXCLKOUT+
38
RXCLKOUT-
39
RXOUT0+
40
RXOUT0-
41
RXOUT1+
42
RXOUT1-
43
RXOUT2+
44
RXOUT2-
45
RXOUT3+
46
RXOUT3-
47
RXOUT4+
48
RXOUT4-
49
[EP]GND
IC5003
DS32EL0124
1
VDD33_1
2
NC_1
3
GPIO0
4
GPIO1
5
DC_B
6
RS
7
VDD25_1
8
NC_2
9
NC_3
10
NC_4
11
GPIO2
12
NC_5
13
NC_6
14
NC_7
15
VDD33_2
16
RXIN0+
17
RXIN0-
18
VDD33_3
19
NC_8
20
NC_9
21
NC_10
22
NC_11
23
NC_12
24
NC_13
25
VDD25_2
26
LF_REF
27
LF_CP
28
VDDPLL
29
NC_14
30
RESET
31
LOCK
32
SDA
33
SCK
34
SMB_CS
35
VDD25_3
36
VDD33_4
37
RXCLKOUT+
38
RXCLKOUT-
39
RXOUT0+
40
RXOUT0-
41
RXOUT1+
42
RXOUT1-
43
RXOUT2+
44
RXOUT2-
45
RXOUT3+
46
RXOUT3-
47
RXOUT4+
48
RXOUT4-
49
[EP]GND
IC5001
DS32EL0124
1
VDD33_1
2
NC_1
3
GPIO0
4
GPIO1
5
DC_B
6
RS
7
VDD25_1
8
NC_2
9
NC_3
10
NC_4
11
GPIO2
12
NC_5
13
NC_6
14
NC_7
15
VDD33_2
16
RXIN0+
17
RXIN0-
18
VDD33_3
19
NC_8
20
NC_9
21
NC_10
22
NC_11
23
NC_12
24
NC_13
25
VDD25_2
26
LF_REF
27
LF_CP
28
VDDPLL
29
NC_14
30
RESET
31
LOCK
32
SDA
33
SCK
34
SMB_CS
35
VDD25_3
36
VDD33_4
37
RXCLKOUT+
38
RXCLKOUT-
39
RXOUT0+
40
RXOUT0-
41
RXOUT1+
42
RXOUT1-
43
RXOUT2+
44
RXOUT2-
45
RXOUT3+
46
RXOUT3-
47
RXOUT4+
48
RXOUT4-
49
[EP]GND
IC5005
DS32EL0124
1
VDD33_1
2
NC_1
3
GPIO0
4
GPIO1
5
DC_B
6
RS
7
VDD25_1
8
NC_2
9
NC_3
10
NC_4
11
GPIO2
12
NC_5
13
NC_6
14
NC_7
15
VDD33_2
16
RXIN0+
17
RXIN0-
18
VDD33_3
19
NC_8
20
NC_9
21
NC_10
22
NC_11
23
NC_12
24
NC_13
25
VDD25_2
26
LF_REF
27
LF_CP
28
VDDPLL
29
NC_14
30
RESET
31
LOCK
32
SDA
33
SCK
34
SMB_CS
35
VDD25_3
36
VDD33_4
37
RXCLKOUT+
38
RXCLKOUT-
39
RXOUT0+
40
RXOUT0-
41
RXOUT1+
42
RXOUT1-
43
RXOUT2+
44
RXOUT2-
45
RXOUT3+
46
RXOUT3-
47
RXOUT4+
48
RXOUT4-
49
[EP]GND
C5073
22uF
10V
22uF
10V
C5067
22uF
10V
10V
OPT
C5068
22uF
10V
10V
OPT
C5069
22uF
10V
10V
OPT
C5070
22uF
10V
10V
OPT
C5071
22uF
10V
10V
OPT
C5072
22uF
10V
10V
OPT
R5048
30
30
1%
R5055
30
30
1%
R5049
30
1%
R5056
30
1%
R5053
30
30
1%
R5057
30
30
1%
R5054
30
30
1%
R5050
30
30
1%
R5052
30
30
1%
R5051
30
30
1%
C5074
C5083
C5075
C5076
C5080
C5081
C5077
C5078
C5079
C5082
72
100
Interface block
LG1152 A0
R5012,C5013 CLOSER TO IC5002
C5019 CLOSER TO IC5001
0.1uF close
to pin15,18
to pin15,18
0.1uF close
to pin25.
to pin25.
22uF and 0.1uF
close to pin25
close to pin25
Send these LVDS
signals to
FPGA
signals to
FPGA
LD 5002 : GPIO1 default value
is power on reset status.
is power on reset status.
C5056 CLOSER TO IC5004
C5053 CLOSER TO IC5005
C5033 CLOSER TO IC5003
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
TXA2P
TXACLKP
C603
0.1uF
16V
0.1uF
16V
TXA3N
TXB2N
R605
10K
VESA
TXB3P
+3.3V_NORMAL
TXB3N
TXA0N
TXB0N
TXACLKN
C601
10uF
25V
10uF
25V
OPT
TXB1P
TXBCLKP
TXA1P
TXBCLKN
TXB4N
TXB2P
TXA1N
TXB4P
TXB1N
TXA0P
R604
3.3K
JEIDA
TXA2N
TXA3P
TXA4N
TXA4P
TXB0P
C602
1000pF
50V
1000pF
50V
L601
TXC1P
TXD3P
TXC4N
TXC0P
TXD4P
TXC4P
TXD2P
TXD0P
TXDCLKN
TXC0N
TXD3N
TXC2P
TXC1N
TXDCLKP
TXD4N
TXC2N
TXC3P
TXD2N
TXCCLKP
TXD1N
TXC3N
TXD1P
TXCCLKN
TXD0N
R614
10K
10BIT
R613
3.3K
8BIT
+3.3V_NORMAL
L604
OLED_MODULE
L605
OLED_MODULE
+20V
+3.5V_ST
Q602
2N7002K
S
D
G
Q601
2N7002K
S
D
G
R619
33
OPT
R618
33
OPT
I2C_BE_SCL1
I2C_BE_SDA1
+3.5V_ST
R624
10K
Q606
MMBT3906(NXP)
1
2
3
R623
10K
RL_ON
R617
0
OLED_MODULE
R630
0
OPT
EXT_COMPENSATION_DONE
R608
33
Q603
2SC3052
E
B
C
Q604
2SC3052
E
B
C
R627
10K
R626
10K
R625
10K
+3.3V_NORMAL
+3.3V_NORMAL
EL_VDD_ON_20V
FPGA_LVDS_INFO
FPGA_LVDS_INFO
R609
4.7K
+3.3V_NORMAL
R601
0
OLED_MODULE
R602
0
OLED_MODULE
R5423
1K
R629
1K
R628
0
OLED_MODULE
+3.5V_ST
R610
3.3K
OPT
C604
0.1uF
50V
0.1uF
50V
C605
0.1uF
50V
0.1uF
50V
C606
0.1uF
50V
0.1uF
50V
+12V
R606
3.3K
OPT
R607
10K
OPT
+3.3V_NORMAL
T_CON_ERROR
C607
10uF
25V
10uF
25V
EL_VDD_ON_20V_MICOM
R611
10K
OPT
20V_DET
R612
0
OPT
P602
FI-RE41S-HF-J-R1500
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
P601
FI-RE51S-HF-J-R1500
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
LVDS_SEL
BCM35230
50
15
LVDS
FHD120Hz LVDS output(51pin+41Pin)
2010.11.03
Bit Selection
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
LOGO_LIGHT_RED
L4102
BLM18PG121SN1D
Q4100
MMBT3904(NXP)
E
B
C
+3.5V_ST
IR
C4104
1000pF
50V
+3.5V_ST
EEPROM_SCL
+3.5V_ST
R4123
100
100
R4107
10K
D4106
20V
ADUC 20S 02 010L
OPT
EEPROM_SDA
R4124
100
100
L4100
BLM18PG121SN1D
D4104
5.6V
AMOTECH CO., LTD.
OPT
D4105
20V
ADUC 20S 02 010L
OPT
C4107
100pF
100pF
50V
R4100
0
0
R4109
10K
OPT
R4110
10K
LOGO_LIGHT
LOGO_LIGHT_WHITE
+3.5V_ST
C4103
0.1uF
16V
0.1uF
16V
LOGO_LIGHT
R4104
0
0
OPT
R4105
0
0
+3.5V_ST
R4103
0
R4108
10K
LOGO_LIGHT
R4101
0
0
OPT
R4106
10K
OPT
C4101
0.1uF
16V
0.1uF
16V
LOGO_LIGHT
Q4101
MMBT3904(NXP)
E
B
C
D4104-*2
5.6V
ESD_LG1152
ADMC 5M 02 200L
200pF
D4104-*1
5.6V
ESD_MTK
ADMC 5M 02 200L
200pF
D4106-*1
20V
ADUC 20S 02 010L
ESD_MTK
10pF
D4105-*1
20V
ADUC 20S 02 010L
ESD_MTK
10pF
R4127
33
LOGO_LIGHT
R4126
33
LOGO_LIGHT
R4128
33
LOGO_LIGHT
R4129
33
LOGO_LIGHT
LOGO_LIGHT_WHITE
LOGO_LIGHT_RED
P4101
12507WR-04L
1
2
3
4
5
P5401
12507WR-06L
IR_6P_with_Eye_Q
1
2
3
4
5
6
7
R4112
1K
LOGO_LIGHT
R4111
1K
LOGO_LIGHT
P5403
12507WR-03L
IR_WITHOUT_EYEQ
1
2
3
4
41
IR / KEY
2011.08.15
Zener Diode is
close to wafer
ESD for LG1152
RGB Sensor
ESD for MTK
IR & EYEQ
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