LG 55EM970V-ZA (CHASSIS:ED23E) Service Manual ▷ View online
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
R11604
10K
C11602
0.1uF
R11603
10K
C11601
0.1uF
R11601
100
100
KEY1
KEY2
R11602
100
100
+3.5V_ST
D11601
5.6V
200pF
D11602
5.6V
200pF
R11605
10K
10K
D11604-*1
5.6V
ESD_LG1152
D11603-*1
5.6V
5.6V
ESD_LG1152
SOC_RX
AV1_CVBS_IN
COMP1_Y
D11606-*2
5.6V
5.6V
ESD_MTK
+3.3V_NORMAL
JK11602
KJA-PH-1-0177-2
3
M3_DETECT
4
M4
5
M5_GND
1
M1
6
M6
AV1_R_IN
COMP1_DET
SOC_TX
AV1_CVBS_DET
D11605-*1
5.6V
5.6V
ESD_LG1152
D11604-*2
5.6V
ESD_MTK
AV1_L_IN
D11606
5.6V
5.6V
OPT
COMP1_Pr
+3.5V_ST
D11606-*1
5.6V
5.6V
ESD_LG1152
D11603
5.6V
5.6V
OPT
D11603-*2
5.6V
5.6V
ESD_MTK
+3.3V_NORMAL
D11605-*2
5.6V
5.6V
ESD_MTK
R11606
10K
COMP1_Pb
JK11601
KJA-PH-1-0177-1
3
M3_DETECT
4
M4
5
M5_GND
1
M1
6
M6
MDS62110218
M102
MDS62110218
M104
MDS62110218
M105
MDS62110218
M109
MDS62110218
M101
MDS62110218
M103
MDS62110218
M106
MDS62110218
M108
MDS62110218
M110
MDS62110218
M107
P11601
12507WS-04L
1
2
3
4
5
P11602
12507WS-04L
1
2
3
4
5
MDS62110218
M111
C11604
18pF
50V
ESD_MTK
ESD_MTK
D11608
5.6V
OPT
JK11602-*1
KJA-PH-1-0177-2
COMP_JACK_GREEN
3
M3_DETECT
4
M4
5
M5_GND
1
M1
6
M6
JK11601-*1
KJA-PH-1-0177-1
AV_JACK_YELLOW
3
M3_DETECT
4
M4
5
M5_GND
1
M1
6
M6
C11603
18pF
50V
ESD_MTK
ESD_MTK
D11607
5.6V
OPT
JP11609
JP11610
JP11611
JP11612
D11604
5.5V
5.5V
D11605
5.5V
5.5V
D11604-*3
ADUC 20S 02 010L
SECOND VARISTOR
D11605-*3
ADUC 20S 02 010L
SECOND VARISTOR
D11609
5.5V
OPT
D11610
5.5V
OPT
JP_GND4
JP_GND3
JP_GND2
JP_GND1
KEY
Zener Diode is
close to wafer
41
IR / KEY
2011.11.21
CVBS 1 PHONE JACK
ESD For MTK
ESD For LG1152
COMPONENT 1 PHONE JACK
RS232C
Close to the jack
Close to the jack
Improve JIG GND
(Request by JIG Part)
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
TX_ENABLE
SIGNAL_DET
C1006
5pF
50V
50V
OPTIC_CABLE_SCL
OPTIC_CABLE_SDA
C1003
0.1uF
+3.5V_ST
C1004
22uF
10V
22uF
10V
OPT
C1005
5pF
50V
50V
BACK_CHANNEL_P
BACK_CHANNEL_N
OPTIC_CABLE_DETECT
+3.5V_ST
+3.5V_ST
R1011
10K
+3.5V_ST
R1015
100
R1001
100
R1002
100
C1007
0.1uF
16V
0.1uF
16V
LINK1B_RXIN_P
LINK1B_RXIN_N
LINK2B_RXIN_N
LINK2B_RXIN_P
LINK5B_RXIN_N
LINK5B_RXIN_P
LINK4B_RXIN_N
LINK4B_RXIN_P
LINK3B_RXIN_N
LINK3B_RXIN_P
R1004
100K
OPTIC_POWER_CTRL
C1009
0.1uF
50V
0.1uF
50V
R1017
0
OPT
R1019
10K
R1020
10K
OPTIC_I2C_PULL_UP
OPTIC_I2C_PULL_UP
Q1000
AO3407A
G
D
S
R1028
33
OPT
EEPROM_SDA
C1010
0.1uF
50V
0.1uF
50V
I2C_CTRL
Q1001
2N7002K
S
D
G
Q1002
2N7002K
S
D
G
C1011
0.1uF
50V
0.1uF
50V
R1023
33
OPT
OPTIC_CABLE_SDA
OPTIC_CABLE_SCL
EEPROM_SCL
C1008
1uF
10V
1uF
10V
R1018
10K
R1003
10K
1/16W
5%
OPT
R1005
10K
1/16W
5%
OPT
D1001
5.5V
R1025
20K
R1022
20K
P1001
FCBJS04RC1-LG
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
71
LVDS_HIGH_MID
2011.04.30
3.3V Power Supply.
Place 22uF and 0.1uF close to
pin 9, pin 10.
Place 22uF and 0.1uF close to
pin 9, pin 10.
Close to Pin B9,B10
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
DEBUG<0>
DEBUG<1>
DEBUG<2>
DEBUG<3>
+2.5V_FPGA
+2.5V_FPGA
R2006
4.7K
4.7K
OPT
R2007
10K
10K
+2.5V_FPGA
+2.5V_FPGA
+2.5V_FPGA
+2.5V_FPGA
C2016
0.47uF
25V
+1.2V_FPGA
+1.2V_FPGA
R2005
0
OPT
IC2002
KIA7029AF
2
G
3
O
1
I
/FPGA_RESET
R2010
10K
R2011
4.7K
C2009
0.1uF
16V
0.1uF
16V
R2002
1K
SW200
JTP-1127WEM
1
2
4
3
OPTIC_FPGA_RESET
/FPGA_RESET
+3.3V_FPGA
+2.5V_FPGA
R2001
330
330
+3.3V_FPGA
R2003
4.7K
R2004
0
0
R2009
10K
/RESET2V5
Q2002
2SC3052
2SC3052
E
B
C
C2005
0.1uF
16V
0.1uF
16V
R2008
10K
Q2001
2SC3052
2SC3052
E
B
C
+2.5V_NORMAL
L2002
L2001
+3.3V_NORMAL
+3.3V_FPGA
+2.5V_FPGA
/RESET2V5
P2005
12507WR-08L
1
2
3
4
5
6
7
8
9
C2008
2.2uF
10V
2.2uF
10V
C2007
2.2uF
10V
FPGA_LINK3B_RXOUT4_N
FPGA_LINK3B_RXOUT4_P
FPGA_LINK3B_RXOUT3_N
FPGA_LINK3B_RXOUT3_P
FPGA_LINK3B_RXOUT2_N
FPGA_LINK3B_RXOUT2_P
FPGA_LINK3B_RXOUT1_N
FPGA_LINK3B_RXOUT1_P
FPGA_LINK3B_RXOUT0_N
FPGA_LINK3B_RXOUT0_P
FPGA_LINK3B_RXCLKOUT_N
FPGA_LINK3B_RXCLKOUT_P
FPGA_LINK4B_RXOUT4_N
FPGA_LINK4B_RXOUT4_P
FPGA_LINK4B_RXOUT3_N
FPGA_LINK4B_RXOUT3_P
FPGA_LINK4B_RXCLKOUT_N
FPGA_LINK4B_RXCLKOUT_P
FPGA_LINK4B_RXOUT2_N
FPGA_LINK4B_RXOUT2_P
FPGA_LINK4B_RXOUT1_N
FPGA_LINK4B_RXOUT1_P
FPGA_LINK4B_RXOUT0_N
FPGA_LINK4B_RXOUT0_P
FPGA_LINK2B_RXOUT3_N
FPGA_LINK2B_RXOUT3_P
FPGA_LINK2B_RXOUT0_N
FPGA_LINK2B_RXOUT0_P
LINK4B_LOCK_N
LINK2B_LOCK_N
LINK1B_LOCK_N
LINK5B_LOCK_N
VCXO2_CTRL
VCXO2_S2/SCL
VCXO2_S0
VCXO2_S1/SDA
P2006
12507WS-04L
OPT
1
2
3
4
5
C2018
0.47uF
16V
C2020
0.47uF
16V
0.47uF
16V
C2021
0.47uF
16V
0.47uF
16V
R2012
33
33
C2006
4.7uF
10V
C2015
4.7uF
10V
C2014
4.7uF
10V
C2019
4.7uF
10V
C2017
4.7uF
10V
C2004
10uF
25V
C2003
10uF
25V
OPT
C2013
10uF
25V
C2012
10uF
25V
C2010
10uF
25V
OPT
C2011
10uF
25V
OPT
IC2001
XC6SLX16-3CSG324I
IO_L54N_M3A11_3
D3
IO_L54P_M3RESET_3
E4
IO_L50P_M3WE_3
E3
IO_L55P_M3A13_3
F6
IO_L55N_M3A14_3
F5
IO_L51P_M3A10_3
F4
IO_L51N_M3A4_3
F3
IO_L53N_M3A12_3
G6
IO_L53P_M3CKE_3
H7
IO_L49P_M3A7_3
H6
IO_L49N_M3A2_3
H5
IO_L44P_GCLK21_M3A5_3
H4
IO_L44N_GCLK20_M3A6_3
H3
IO_L47P_M3A0_3
J7
IO_L47N_M3A1_3
J6
IO_L45N_M3ODT_3
K6
IO_L40P_M3DQ6_3
J3
IO_L42N_GCLK24_M3LDM_3
K3
IO_L42P_GCLK25_TRDY2_M3UDM_3
K4
IO_L43N_GCLK22_IRDY2_M3CASN_3
K5
IO_L43P_GCLK23_M3RASN_3
L5
IO_L45P_M3A3_3
L7
IO_L31P_3
L6
IO_L39P_M3LDQS_3
L4
IO_L83P_3
C2
IO_L83N_VREF_3
C1
IO_L52P_M3A8_3
D2
IO_L52N_M3A9_3
D1
IO_L50N_M3BA2_3
E1
IO_L48P_M3BA0_3
F2
IO_L48N_M3BA1_3
F1
IO_L46N_M3CLKN_3
G1
IO_L46P_M3CLK_3
G3
IO_L41N_GCLK26_M3DQ5_3
H1
IO_L41P_GCLK27_M3DQ4_3
H2
IO_L40N_M3DQ7_3
J1
IO_L38P_M3DQ2_3
K2
IO_L38N_M3DQ3_3
K1
IO_L37N_M3DQ1_3
L1
IO_L37P_M3DQ0_3
L2
IO_L36N_M3DQ9_3
M1
IO_L35P_M3DQ10_3
N2
IO_L35N_M3DQ11_3
N1
IO_L1N_VREF_3
N3
IO_L34N_M3UDQSN_3
P1
IO_L34P_M3UDQS_3
P2
IO_L2N_3
P3
IO_L33N_M3DQ13_3
T1
IO_L33P_M3DQ12_3
T2
IO_L32N_M3DQ15_3
U1
IO_L32P_M3DQ14_3
U2
IO_L36P_M3DQ8_3
M3
IO_L2P_3
P4
IO_L1P_3
N4
IO_L31N_VREF_3
M5
IO_L39N_M3LDQSN_3
L3
VCCO_3_1
E2
VCCO_3_2
G4
VCCO_3_3
J2
VCCO_3_4
J5
VCCO_3_5
M4
VCCO_3_6
R2
IC2001
XC6SLX16-3CSG324I
TCK
A17
TDI
D15
TMS
B18
TDO
D16
SUSPEND
R16
CMPCS_B_2
P13
DONE_2
V17
PROGRAM_B_2
V2
GND_1
A1
GND_2
A18
GND_4
B13
GND_3
B7
GND_6
C16
GND_5
C3
GND_8
D10
GND_7
D5
GND_9
E15
GND_12
G12
GND_13
G17
GND_10
G2
GND_11
G5
GND_15
H10
GND_14
H8
GND_18
J11
GND_19
J15
GND_16
J4
GND_17
J9
GND_21
K10
GND_20
K8
GND_23
L11
GND_22
L9
VCCAUX_1
B1
VCCAUX_2
B17
VCCAUX_5
E14
VCCAUX_3
E5
VCCAUX_4
E9
VCCAUX_6
G10
VCCAUX_7
J12
VCCAUX_8
K7
VCCAUX_9
M9
VCCAUX_11
P10
VCCAUX_12
P14
VCCAUX_10
P5
VCCINT_1
G7
VCCINT_3
H11
VCCINT_2
H9
VCCINT_5
J10
VCCINT_4
J8
VCCINT_7
K11
VCCINT_6
K9
VCCINT_9
L10
VCCINT_8
L8
VCCINT_11
M12
VCCINT_10
M7
GND_26
M17
GND_24
M2
GND_25
M6
GND_27
N13
GND_28
R1
GND_31
R14
GND_32
R18
GND_29
R4
GND_30
R9
GND_33
T16
GND_35
U12
GND_34
U6
GND_36
V1
GND_37
V18
IC2001
XC6SLX16-3CSG324I
IO_L9P_0
E7
IO_L9N_0
E8
IO_L7P_0
F7
IO_L7N_0
E6
IO_L32P_0
G8
IO_L32N_0
F8
IO_L40P_0
G11
IO_L40N_0
F10
IO_L42P_0
F11
IO_L42N_0
E11
IO_L47P_0
D12
IO_L47N_0
C12
IO_L50P_0
C13
IO_L50N_0
A13
IO_L51P_0
F12
IO_L51N_0
E12
IO_L5P_2
U15
IO_L5N_2
V15
IO_L19P_2
T12
IO_L19N_2
V12
IO_L20P_2
N10
IO_L20N_2
P11
IO_L22P_2
M10
IO_L22N_2
N9
IO_L15P_2
M11
IO_L15N_2
N11
IO_L44P_2
N7
IO_L44N_2
P8
IO_L40P_2
M8
IO_L40N_2
N8
IO_L47P_2
N6
IO_L47N_2
P7
Decouplingcapacitors forVCCINT
XILINX JTAG HDR FOR CONFIG OR CHIPSCOPE
Decouplingcapacitors forVCCO Bank3
Decouplingcapacitors forVCCAUX
FPGA Reset Level Shifter (3.3V to 2.5V)
From DES IC to FPGA
For Debug requested NSC
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
R3110
4.7K
+2.5V_FPGA
+2.5V_FPGA
+2.5V_FPGA
FPGA_SPI_DO
FPGA_SPI_DI
FPGA_SPI_CLK
+2.5V_FPGA
+2.5V_FPGA
R3109
22
R3111
0
/RESET2V5
R3108
0
OPT
R3103
10K
R3105
10K
OPT
R3106 1K
R3104 1K
OPT
FPGA_SPI_CZ
FPGA_LINK5B_RXOUT4_N
FPGA_LINK5B_RXOUT4_P
FPGA_LINK5B_RXOUT3_N
FPGA_LINK5B_RXOUT3_P
FPGA_LINK5B_RXOUT2_N
FPGA_LINK5B_RXOUT2_P
FPGA_LINK5B_RXOUT1_N
FPGA_LINK5B_RXOUT1_P
FPGA_LINK5B_RXOUT0_N
FPGA_LINK5B_RXOUT0_P
FPGA_LINK5B_RXCLKOUT_N
FPGA_LINK5B_RXCLKOUT_P
FPGA_LINK2B_RXOUT4_N
FPGA_LINK2B_RXOUT4_P
FPGA_LINK2B_RXOUT2_N
FPGA_LINK2B_RXOUT1_N
FPGA_LINK2B_RXOUT1_P
FPGA_LINK2B_RXCLKOUT_N
FPGA_LINK2B_RXCLKOUT_P
FPGA_LINK2B_RXOUT2_P
LINK3B_LOCK_N
L3103
+2.5V_NORMAL
VCXO1_CLK_Y
VCXO1_CTRL
BACK_CHANNEL_P
BACK_CHANNEL_N
C3114
0.1uF
C3115
0.1uF
R3132
22
+2.5V_VCXO
VCXO1_CLK_Y
VCXO1_CTRL
C3101
0.1uF
16V
0.1uF
16V
C3112
24pF
50V
50V
OPT
R3131
22
R3127
2.2K
R3130
22
R3125
100K
100K
R3126
240K
C3118
0.1uF
16V
0.1uF
16V
VCXO2_S0
C3119
0.1uF
16V
0.1uF
16V
X3003
27MHz
27MHz
4
GND_2
1
X-TAL_1
2
GND_1
3
X-TAL_2
R3128
2.2K
VCXO2_S1/SDA
+1.8V_VCXO
+2.5V_VCXO
C3113
24pF
50V
50V
OPT
VCXO2_S2/SCL
+2.5V_VCXO
VCXO2_CLK_Y
R3124
0
VCXO2_CTRL
P3102
PH254ST-1*3P1-GP
OPT
1
2
3
R3129
2.2K
C3111
0.1uF
16V
0.1uF
16V
R3134
22
L3108
CIS21J121
OPT
+3.3V_FPGA
L3107
CIS21J121
R5421
10K
10K
C3104
0.47uF
16V
C3105
0.47uF
16V
C3106
0.47uF
16V
0.47uF
16V
+1.8V_VCXO
+2.5V_VCXO
C3103
4.7uF
10V
C3102
10uF
25V
IC3003
CDCE925PWR-AB(12.288MHZ+/-650PPPM)
3
VDD
2
S0
4
VCTR
1
XIN/CLK
6
VDDOUT_1
5
GND_1
7
Y4
8
Y5
9
VDDOUT_2
10
Y3
11
Y2
12
GND_2
13
Y1
14
S2/SCL
15
S1/SDA
16
XOUT
C3116
2200pF
50V
X3102
74.2125MHZ
FS_50ppm
4
VDD
1
VIN
2
GND
3
CLK
IC2001
XC6SLX16-3CSG324I
IO_L62P_D5_2
R3
IO_L65P_INIT_B_2
U3
IO_L63P_2
T4
IO_L49P_D3_2
U5
IO_L48N_RDWR_B_VREF_2
T5
IO_L43N_2
V7
IO_L43P_2
U7
IO_L46N_2
T7
IO_L41N_VREF_2
V8
IO_L41P_2
U8
IO_L31N_GCLK30_D15_2
T8
IO_L30N_GCLK0_USERCCLK_2
V10
IO_L30P_GCLK1_D13_2
U10
IO_L29N_GCLK2_2
T10
IO_L23P_2
U11
IO_L16N_VREF_2
T11
IO_L14N_D12_2
V13
IO_L14P_D11_2
U13
IO_L3N_MOSI_CSI_B_MISO0_2
T13
IO_L12N_D2_MISO3_2
V14
IO_L12P_D1_MISO2_2
T14
IO_L1N_M0_CMPMISO_2
T15
IO_L2N_CMPMOSI_2
V16
IO_L2P_CMPCLK_2
U16
IO_L45N_2
V6
IO_L65N_CSO_B_2
V3
IO_L63N_2
V4
IO_L49N_D4_2
V5
IO_L32N_GCLK28_2
V9
IO_L45P_2
T6
IO_L23N_2
V11
IO_L62N_D6_2
T3
IO_L1P_CCLK_2
R15
IO_L3P_D0_DIN_MISO_MISO1_2
R13
IO_L13P_M1_2
N12
IO_L13N_D10_2
P12
IO_L16P_2
R11
IO_L29P_GCLK3_2
R10
IO_L31P_GCLK31_D14_2
R8
IO_L32P_GCLK29_2
T9
IO_L46P_2
R7
IO_L48P_D7_2
R5
IO_L64P_D8_2
N5
IO_L64N_D9_2
P6
VCCO_2_1
P9
VCCO_2_3
R12
VCCO_2_2
R6
VCCO_2_6
U14
VCCO_2_4
U4
VCCO_2_5
U9
FPGA_SPI_CLK
FPGA_SPI_DO
FPGA_SPI_DI
+2.5V_FPGA
L3102
CIS21J121
R3113
1K
1/16W
1%
OPT
C3107
0.1uF
L3101
CIS21J121
OPT
R3116
1K
1/16W
1%
OPT
+3.3V_FPGA
FPGA_SPI_CZ
R3114
22
R3115
2.4K
R3112
1.8K
IC3101
W25Q40CLSNIG
3
WP[IO2]
2
DO[IO1]
4
GND
1
CS
5
DI[IO0]
6
CLK
7
HOLD[IO3]
8
VCC
X3102-*1
74.2125MHZ
FS_10ppm
4
VDD
1
VIN
2
GND
3
CLK
Decouplingcapacitors forVCCO Bank2
From DES IC to FPGA
Mode Pins --> determine configuration mode
Parallel configuration mode bus is auto-detected by the configuration logic.
M[1:0] = 10
CCLK Direction : Input
Bus Width : 8, 16
Parallel configuration mode bus is auto-detected by the configuration logic.
M[1:0] = 10
CCLK Direction : Input
Bus Width : 8, 16
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