DOWNLOAD LG 50PZ950B-SA (CHASSIS:PB12A) Service Manual ↓ Size: 13.62 MB | Pages: 90 in PDF or view online for FREE

Model
50PZ950B-SA (CHASSIS:PB12A)
Pages
90
Size
13.62 MB
Type
PDF
Document
Service Manual
Brand
Device
TV / Plasma
File
50pz950b-sa-chassis-pb12a.pdf
Date
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LG 50PZ950B-SA (CHASSIS:PB12A) Service Manual ▷ View online

GP3_PDP Block Diagram (#2 3D Block) 
I2C
L/R DETECT
3DF_ASIC RESET
LVDS 2Ch
DDR2
(256Mbit) 
3D :
1920x1080/60Hz
(S/S, T/B, C/B, F/S)
1920x1080/48Hz
(F/S)
X-tal
(25MHz)
Serial_Flash
(2Mbit)
LVDS 2Ch
Left (2D):
1920x1080/60Hz
LVDS
 (
 8
0
Pin
 )
LVDS 2Ch
3D_SYNC_OUT
■ Processing
ƒ LVDS-Rx , Dual Link 10 bit (25~85MHz)
ƒ LVDS-Tx , Quad Link 10 bit (25~85MHz)
ƒ DDR2-PHY : 
333MHz (Max.350MHz)
(DDR2 x16 1ea, 256Mb)
ƒ GPIO#32
BCM35230
BCM35230
3DF_ASIC
LG8300
3DF_ASIC
LG8300
PDP
PDP
3D_SYNC
EMITTER_PULSE
Right :
1920x1080/60Hz
1920x1080
60Hz
PO_RST_N
GPIO[2]
I2C
I2C_M
RF_Tx
RF_Tx
RF_Shutter_Glasses
3D_GPIO
3
Main Board for GP3 PDP
1
2
3
4
5
Power 18pin
LVDS 80P
IR/Soft touch
Speaker 4pin
RF Emitter
1
Main processor, DDR Memory
Flash Memory
2
3
4
3D Block
Micom
Audio AMP (10W+10W)
5
HDMI switch (4:1)
Power Board
Main
Y Board
Z Board
ASIC
X board
50PZ950B-SA model image
50PZ950B-SA model block diagram
Emitter
Set layout
Power Board
Main
Y Board
Z Board
ASIC
X board
60PZ950B-SA model image
60PZ950B-SA model block diagram
Emitter
BCM35230 I2C MAP
BSCCLKA
MICOM
(uPD78F0514)
0x52
MICOM
(uPD78F0514)
0x52
BSCDATAA
(AA2)
(AA3)
NVRAM
(M24M01)
0xA8
NVRAM
(M24M01)
0xA8
RDB/GPIO
TDB/GPIO
(H3)
(H2)
<
SCL_2>
<
SDA_2 >
HDMI SW
(SIL9287)
0xB0
HDMI SW
(SIL9287)
0xB0
+3.3V
+3.3V
GPIO_1
GPIO_0
(A15)
(C16)
<
SCL_0 >
<
SDA_0 >
+3.3V
<
SCL_1 >
<
SDA_1 >
WIRELESS
(P901)
0x20
WIRELESS
(P901)
0x20
CHB
PROCESSOR
(LG1140)
0xF2
CHB
PROCESSOR
(LG1140)
0xF2
CHB
DECODER
(TW9910)
0x88
CHB
DECODER
(TW9910)
0x88
AUDIO AMP
(STA368)
0x38
AUDIO AMP
(STA368)
0x38
I2SWS_IN
I2SSD_IN/GPIO
(F4)
(G5)
<
SCL_3>
<
SDA_3>
+3.3V
HW1
HW4
HW2
SW1
I2SSCK_OUTC/GPIO
I2SWS_OUTC/GPIO
(E2)
(F2)
PDP MODULE
(50R3/60R3)
2D : 0x1C
3D : 0x74
PDP MODULE
(50R3/60R3)
2D : 0x1C
3D : 0x74
<
MOD_SCL >
<
MOD_SDA >
+3.3V
SW2
PORT    BALL     HW_C             SW_C
DEVICE/SLAVE ADDRESS
3D Formatter
(LG8300)
IND : 0x76
DIR : 0x3C
3D Formatter
(LG8300)
IND : 0x76
DIR : 0x3C
CH1
CH1
CH4
CH4
CH2
CH2
CH5
CH5
CH6
CH6
BSC_S_SCL
BSC_S_SDA
HW3
+3.3V
CH3
CH3
<
RGB_EDID_SCL >
<
RGB_EDID_SDA >
(H4)
(H5)
RGB EDID
(AT24C02)
0xA0
RGB EDID
(AT24C02)
0xA0
BBS JIG
BBS JIG
H/NIM MAIN
TUNER
A_DEMOD : 0x10
MOPLL : 0xC0
H/NIM MAIN
TUNER
A_DEMOD : 0x10
MOPLL : 0xC0
CHB F/NIM
SUB TUNER
(Si2173)
0xC6
CHB F/NIM
SUB TUNER
(Si2173)
0xC6
CHB F/NIM
SUB DEMOD
(LGDT3305)
0xB2
CHB F/NIM
SUB DEMOD
(LGDT3305)
0xB2
BRAZIL
F/NIM
DEMOD
0x30 
BRAZIL
F/NIM
DEMOD
0x30 
■ GP3 I2C 채널 변경
1. HDMI I2C 채널 변경
: H/W2 → S/W1 변경
2. CHB I2C 채널 변경
: S/W1 -> H/W4 변경
3. C0 Chip HW I2C 추가 및
DEMOD 동작 안정성에 따른
I2C 채널 Swap
: NVM, AMP, HDMI SW(CH4) 
↔ DEMOD, CHB(CH5)
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