LG 50PG6000-ZA (CHASSIS:PD81A) Service Manual ▷ View online
- 21 -
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TR
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DT
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A
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[A
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D
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[A
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[V
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11]
SI
D
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V
B
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L
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[V
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O
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1
]
F
LI
10306
MI
C
O
M
TU
N
E
R
TR
N
e
t
M
S
P
4458
M
S
P
4458
SI
F
AM
A
U
D
IO
I2
S
Mu
x
e
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A
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d
io
Mu
x
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A
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io
[A
UD
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UT
1
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TR
A
d
j
1:Audio R out (TV)
2:audio R in
3:audio L out (TV)
4:audio GND
5:blue GND
6:audio L in
7:Blue
8:SCART ID
9:green GND
10:data 2 (NC)
11:Green
12:data1 (NC)
13: Link (red GND)
14:data GND (NC)
15:Red
16:SCART FB
17:video GND
18:RGB Control GND
19:CVBS out (TV out)
20:CVBS in
21:safety GND
22:GND
23:GND
1:Audio R out (DTV)
2:audio R in
3:audio L out (DTV)
4:audio GND
5:GND
6:audio L in
7:NC
8:function select
9: NC
10:data 2 (NC)
11:NC
12:data1 (NC)
13: Link
14:data GND (NC)
15: NC
16: NC
17:video GND
18:GND
19:CVBS out (DTV out)
20:CVBS in
21:safety GND
22:GND
23:GND
SCART 1
SCART 2
- 22 -
BlockDiagram
( Component & RGB & HDMI)
COMP_Y
COMP_PB
COMP_PR
VGA_R
VGA_B
VGA_G
HSYNC
VSYNC
EDID
EEPROM
AT24C02BN
D_SUB_I2C
COMP_L
COMP_R
PC L,R
[A3P]
[B3P]
[C3P]
[VXO_D0]
[AUD_IN_L3]
[AVS]
[AHS_ACS]
[A1P]
Level Adj
Level Adj
[AUD_IN_R3]
COMP Link
[B1P]
[C1P]
74HC14D
Schmitt triggering
Usage : BUF
[VXO_HS]
RGB Link
[AUD_IN_L5,R5]
HDMI 2 TMDS[8bit]
DDC HDMI2 I2C
EDID
AT24C02BN
HDMI 3 TMDS[8bit]
DDC HDMI3 I2C
EDID
AT24C02BN
HDMI SW TMDS[8bit]
HDMI I2C [SW]
HDMI EQ Ctrl
[VXO_D6]
[GPIOA0]
[GPIOA1]
HDMI Select 1
HDMI Select 2
CEC_REMOTE
[GPIOB1]
[2WIRE_S1]
[2WIRE_S0]
[DSDA1,DSCL1]
HDMI SW TMDS[8bit]
DDC HDMI4 I2C
EDID
AT24C02BN
[2WIRE_S2]
[BRX]
[ARX]
[VXO_D20]
[VXO_D21]
HDMI1 5V DET
HDMI3 5V DET
HDMI4 5V DET
[VXO_CLK]
HP DET S/W4
[VXI_D23]
HP DET S/W1
HP DET S/W3
[HDMI_B_HPD]
[HDMI_A_HPD]
[VXO_D22]
FET Bi-BUF
NLASB3157
IC502
2 RX
CHAPLIN RX
UCOM RX
3 TX
UCOM TX
CHAPLIN TX
6 RX
4TX
G-probe
FLI10306
MICOM
MICOM
TMDS351PAG
IC201
MAX3232CDR
IC101
HDMI 2 TMDS[8bit]
DDC HDMI2 I2C
EDID
AT24C02BN
HDMI2 5V DET
HP DET S/W2
[VXO_D19]
- 23 -
BlockDiagram
( FE & PCMCIA)
CI_TS[0:7]
Tuner
(TDFV-G135D1)
TU301
74LVC541A(PW)
Buffer
IC402
PCMCIA
Card
74LVC542A5
Bi-Buffer
IC405
HOST DATA[0:7]
FE_TS[0:7]
FLI10306
HOST Address[1:24]
HOST DATA[0:15]
FLASH WP Ctrl
[OOB_CTX]
RESET
[GPIOE7]
HOST Write Enable
[POD_WE_HOST_WR]
HOST Out Enable
[POD_OE_HOST_RD]
HOST Chip Enable
[HOST_BOOD_CS_N]
CI DATA[0:7]
[POD_DIR_N]
CI DATA Dir Select
CI Detect
[POD_DETECT_N]
CI Detect
TS_IN[0:7]
74LCX244MTC
Buffer
IC406
HOST Address[0:3]
POD Address[4:7]
CI Address[0:7]
74LCX244MTC
Buffer
IC407
HOST Address[10:13]
POD Address[8;9;14]
HOST Address[4]
74LCX244MTC
Buffer
IC408
REG
CI Detect
CI Detect
CI Address[8:14]
CI Detect
[POD_OE_HOST_RD]
HOST Out Enable
CI Out Enable
HOST Write Enable
CI Write Enable
HOST Address[6]
CI IORD
HOST Address[5]
CI IOWR
FE_TS_DATA_VAL
CI_MIVAL
FE_TS_DATA_SYN
CI_MISTRT
FE_TS_DATA_CLK
CI_MICLK
Tuner
(TDFV-G135D1)
TU301
TPS2042BDRG4
Power
Distributer
IC301
5V
600mA
5V
5V_ANN_MNT
5V_ANN_CTL
[AUDO_I2SB_DAT1]
[AUDO_I2SB_DAT2]
S29GL256N10TFI020
NOR Flash
FLI10306
MICOM
TS[0], CLK, SY, VAL
- 24 -
Mute
CTRL
[TR]
BlockDiagram
(Audio & etc)
SPDIF_OUT
MUTE_LINE
NTP3000
Digital AMP
Bit CLK
Mute
CTRL
[TR]
LR CLK
SW_RESET
LPF
LPF
Level
Adj
Level
Adj
Level
Adj
Scart1 L/R
Scart2 L/R
Comp L/R
SIDE L/R
PC L/R
[AUD_IN_L/R 1] Ch. 3
[AUD_IN_L/R 1] Ch. 4
[AUD_IN_L/R 1] Ch. 5
Audio Master CLK
LR Ch. Data
[AUD_MCLK0]
[AUDO_I2SA_BCLK]
[AUDO_I2SA_WCLK]
[AUDO_I2SA_DAT0]
[AUD_OUT1 L/R]
[AUDO_SPDIR_OUT]
Tuner
(TDFV-G135D1)
TU301
AM AUDIO
TR BUF
MUTE_LINE_DTV
TR BUF
TR BUF
SCART 1
SCART 2
TV LR OUT
DTV/MNT LR OUT
16V
[FAULT]
AUDIO_MUTE
[VXO_D5]
[RESET]
I2C 3.3V
TPY : 10W+10W
MAX : 15W+15W
TPS2042BDRG4
Power
Distributer
IC901
5V
USB DP/DM
5V
600mA
FLI10306
MICOM
MICOM
USB20-PWE
USB20-OC
Sound IF
TR BUF
MSP
4458
Bit CLK, LR CLK,
CR Ch Data
MPE
Level
Adj
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