DOWNLOAD LG 47LH85 (CHASSIS:LA92F) Service Manual ↓ Size: 39.68 MB | Pages: 76 in PDF or view online for FREE

Model
47LH85 (CHASSIS:LA92F)
Pages
76
Size
39.68 MB
Type
PDF
Document
Service Manual
Brand
Device
TV / LCD
File
47lh85-chassis-la92f.pdf
Date

LG 47LH85 (CHASSIS:LA92F) Service Manual ▷ View online

THE    SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE    SYMBOL MARK OF THE SCHEMETIC.
DDR2
SDDR_A[4]
BDDR2_D[15]
TDDR_D[4]
SDDR_A[0]
TDDR_A[8]
SDDR_D[8]
TDDR_D[12]
ADDR2_D[0]
TDDR_D[9]
ADDR2_DQM1_P
SDDR_DQS0_P
BDDR2_D[3]
ADDR2_D[0-15]
TDDR_D[8]
BDDR2_A[0]
ADDR2_A[2]
SDDR_A[2]
BDDR2_A[10]
TDDR_D[11]
BDDR2_BA[1]
SDDR_CK
TDDR_A[10]
ADDR2_D[13]
ADDR2_D[13]
TDDR_D[10]
SDDR_D[3]
ADDR2_D[9]
ADDR2_A[0]
TDDR_D[7]
ADDR2_DQS0_N
ADDR2_A[8]
ADDR2_D[0]
/BDDR2_MCLK
SDDR_D[8]
ADDR2_A[10]
TDDR_BA[0]
TDDR_A[7]
BDDR2_A[3]
TDDR_A[11]
BDDR2_A[5]
SDDR_D[11]
ADDR2_A[12]
SDDR_A[4]
BDDR2_D[13]
ADDR2_A[1]
/SDDR_CK
ADDR2_DQS1_P
SDDR_D[6]
ADDR2_D[5]
TDDR_D[13]
ADDR2_A[0]
BDDR2_D[13]
ADDR2_A[5]
BDDR2_A[11]
ADDR2_D[12]
BDDR2_D[14]
BDDR2_D[11]
BDDR2_A[2]
SDDR_A[12]
TDDR_D[9]
SDDR_D[2]
ADDR2_A[5]
ADDR2_BA[1]
ADDR2_A[12]
SDDR_A[5]
BDDR2_D[1]
ADDR2_CKE
ADDR2_A[2]
BDDR2_A[7]
BDDR2_D[7]
ADDR2_A[7]
TDDR_D[14]
SDDR_A[11]
ADDR2_D[6]
TDDR_A[2]
SDDR_A[0]
SDDR_D[4]
BDDR2_D[0]
BDDR2_A[4]
BDDR2_A[12]
BDDR2_D[6]
BDDR2_D[1]
SDDR_D[5]
BDDR2_D[3]
BDDR2_DQM1_P
SDDR_D[0-15]
SDDR_D[0]
ADDR2_A[1]
BDDR2_A[5]
BDDR2_D[2]
ADDR2_DQM0_P
BDDR2_A[7]
TDDR_D[7]
BDDR2_D[10]
BDDR2_DQS0_P
ADDR2_D[2]
/TDDR_CAS
ADDR2_D[8]
ADDR2_D[10]
BDDR2_A[4]
SDDR_D[1]
SDDR_D[14]
TDDR_A[6]
TDDR_A[9]
ADDR2_A[6]
TDDR_D[1]
BDDR2_A[12]
TDDR_D[15]
BDDR2_D[5]
BDDR2_CKE
SDDR_D[13]
BDDR2_D[7]
SDDR_A[9]
SDDR_D[14]
TDDR_D[8]
ADDR2_BA[0]
BDDR2_D[4]
TDDR_D[5]
BDDR2_DQM0_P
SDDR_D[12]
SDDR_A[6]
SDDR_A[8]
TDDR_D[13]
ADDR2_ODT
SDDR_D[4]
SDDR_A[2]
SDDR_D[10]
BDDR2_D[14]
ADDR2_D[15]
TDDR_A[4]
SDDR_D[11]
/ADDR2_MCLK
BDDR2_D[12]
/SDDR_CAS
ADDR2_DQS1_N
ADDR2_D[12]
SDDR_A[10]
SDDR_A[1]
SDDR_D[1]
BDDR2_A[11]
BDDR2_DQS0_N
ADDR2_D[8]
SDDR_BA[0]
BDDR2_A[1]
ADDR2_D[15]
SDDR_A[9]
BDDR2_D[9]
TDDR_D[6]
ADDR2_D[3]
ADDR2_DQS0_P
ADDR2_D[14]
BDDR2_A[6]
/ADDR2_CAS
SDDR_A[7]
TDDR_D[12]
TDDR_A[8]
BDDR2_BA[0]
TDDR_D[11]
ADDR2_A[11]
TDDR_A[0-12]
SDDR_D[10]
BDDR2_A[0]
BDDR2_D[8]
BDDR2_DQS1_P
ADDR2_D[10]
ADDR2_A[7]
SDDR_A[6]
TDDR_D[3]
BDDR2_D[9]
TDDR_CKE
SDDR_DQS1_N
ADDR2_D[14]
ADDR2_A[11]
TDDR_A[3]
TDDR_A[7]
BDDR2_D[5]
BDDR2_A[8]
/BDDR2_WE
BDDR2_ODT
BDDR2_D[0-15]
SDDR_A[3]
TDDR_D[0]
BDDR2_D[15]
SDDR_ODT
SDDR_A[7]
TDDR_D[1]
SDDR_DQM1_P
SDDR_D[13]
ADDR2_A[4]
TDDR_D[5]
TDDR_A[0]
ADDR2_D[5]
TDDR_A[12]
SDDR_D[5]
TDDR_D[15]
ADDR2_D[7]
SDDR_A[0-12]
SDDR_BA[1]
/TDDR_MCLK
SDDR_D[0]
TDDR_D[0-15]
SDDR_D[7]
BDDR2_A[6]
ADDR2_D[6]
SDDR_A[11]
SDDR_A[8]
SDDR_A[5]
SDDR_D[6]
TDDR_MCLK
TDDR_D[2]
TDDR_A[9]
ADDR2_A[9]
SDDR_D[15]
ADDR2_D[7]
SDDR_A[3]
SDDR_DQS1_P
SDDR_A[12]
SDDR_D[15]
BDDR2_A[0-12]
TDDR_D[10]
TDDR_D[6]
BDDR2_A[9]
TDDR_DQM0_P
TDDR_A[1]
ADDR2_D[1]
BDDR2_A[10]
/ADDR2_WE
BDDR2_D[8]
/TDDR_WE
/SDDR_WE
ADDR2_A[4]
ADDR2_A[3]
ADDR2_A[10]
BDDR2_A[3]
ADDR2_MCLK
TDDR_DQS0_N
TDDR_DQS1_P
TDDR_A[3]
SDDR_D[9]
ADDR2_D[1]
BDDR2_DQS1_N
SDDR_A[1]
TDDR_DQS0_P
ADDR2_A[0-12]
BDDR2_D[4]
TDDR_A[0]
/BDDR2_CAS
TDDR_D[14]
BDDR2_D[12]
SDDR_DQM0_P
BDDR2_D[6]
BDDR2_D[0]
SDDR_D[12]
/BDDR2_RAS
BDDR2_D[10]
TDDR_A[10]
TDDR_A[4]
TDDR_D[4]
TDDR_A[2]
TDDR_D[0]
ADDR2_D[2]
SDDR_DQS0_N
/ADDR2_RAS
BDDR2_A[2]
/SDDR_RAS
TDDR_A[5]
BDDR2_A[1]
BDDR2_MCLK
SDDR_D[9]
SDDR_D[2]
BDDR2_D[2]
BDDR2_A[8]
SDDR_CKE
TDDR_A[6]
ADDR2_D[9]
BDDR2_D[11]
TDDR_D[3]
ADDR2_D[4]
ADDR2_D[11]
TDDR_BA[1]
ADDR2_D[11]
TDDR_A[5]
TDDR_D[2]
ADDR2_A[8]
TDDR_DQM1_P
ADDR2_A[9]
SDDR_D[7]
BDDR2_A[9]
/TDDR_RAS
ADDR2_A[3]
SDDR_A[10]
TDDR_DQS1_N
ADDR2_D[3]
SDDR_D[3]
TDDR_A[12]
ADDR2_D[4]
ADDR2_A[6]
TDDR_A[11]
TDDR_A[1]
ADDR2_BA[2]
SDDR_BA[2]
BDDR2_BA[2]
TDDR_BA[2]
R239
56
C237
0.1uF
R240
56
AR204
56
AR206
56
R238
56
C224
0.1uF
C231
0.1uF
C221
0.1uF
AR209
56
AR202
56
C229
10uF
R220 56
R215
56
R205
56
C230
0.1uF
C217
1000pF
R233
56
R209
56
C212
10uF
C219
0.1uF
C201
1000pF
C226
0.1uF
C210
0.1uF
C223
0.1uF
C202
10uF
R223
1K
1%
+1.8V_S_DDR
C236
0.1uF
R234
56
R213
56
R216
56
+1.8V_S_DDR
AR207
56
C240
0.1uF
R218
56
R204
1K
1%
R214
56
R219
56
R222
1K
1%
C207
0.1uF
C233
0.1uF
C228
0.1uF
C213
0.1uF
+1.8V_S_DDR
AR212
56
R228
56
AR200
56
AR203
56
C209
0.1uF
R241
56
R232
56
R211
56
R237
56
C216
0.1uF
C238
0.1uF
AR211
56
AR208
56
R210
56
+1.8V_S_DDR
C204
0.1uF
R227
56
L200
BLM18PG121SN1D
R226
56
AR210
56
C234
0.1uF
C241
1000pF
C206
0.1uF
R212
56
R229
56
+1.8V_DDR
AR201
56
R203
1K
1%
C205
0.1uF
AR213
56
C203
0.1uF
C239
0.1uF
R217
56
C242
0.1uF
R236
56
C214
0.1uF
C211
0.1uF
R242
56
C200
0.1uF
R201
150
OPT
R244
150
OPT
C232
0.1uF
R243
1K
1%
R235
56
C208
0.1uF
AR205
56
+1.8V_S_DDR
C222
10uF
+1.8V_S_DDR
C218
0.1uF
C215
0.1uF
+1.8V_S_DDR
C220
0.1uF
R206
56
C235
0.1uF
R246
1K
1%
+1.8V_S_DDR
R221
56
R207
33
R208
33
R231
33
R230
33
R200
0
OPT
R202
56
OPT
R225
0
OPT
R224
56
OPT
IC100
MSD3159GV
EAN60351601
B_DDR2_A0
T26
B_DDR2_A1
AF26
B_DDR2_A2
T25
B_DDR2_A3
AF23
B_DDR2_A4
T24
B_DDR2_A5
AE23
B_DDR2_A6
R26
B_DDR2_A7
AD22
B_DDR2_A8
R25
B_DDR2_A9
AC22
B_DDR2_A10
AD23
B_DDR2_A11
R24
B_DDR2_A12
AE22
B_DDR2_BA0
AC23
B_DDR2_BA1
AC24
B_DDR2_BA2
AB22
B_DDR2_MCLK
V25
/B_DDR2_MCLK
V24
B_DDR2_CKE
AB23
B_DDR2_ODT
U26
/B_DDR2_RAS
U25
/B_DDR2_CAS
U24
/B_DDR2_WE
AB24
B_DDR2_DQS0
AB26
B_DDR2_DQS1
AA26
B_DDR2_DQM0
AC25
B_DDR2_DQM1
AC26
B_DDR2_DQSB0
AB25
B_DDR2_DQSB1
AA25
B_DDR2_DQ0
W25
B_DDR2_DQ1
AE26
B_DDR2_DQ2
W24
B_DDR2_DQ3
AF24
B_DDR2_DQ4
AF25
B_DDR2_DQ5
V26
B_DDR2_DQ6
AE25
B_DDR2_DQ7
W26
B_DDR2_DQ8
Y26
B_DDR2_DQ9
AD25
B_DDR2_DQ10
Y25
B_DDR2_DQ11
AE24
B_DDR2_DQ12
AD26
B_DDR2_DQ13
Y24
B_DDR2_DQ14
AD24
B_DDR2_DQ15
AA24
A_MVREF
D15
A_DDR2_A0
C13
A_DDR2_A1
A22
A_DDR2_A2
B13
A_DDR2_A3
C22
A_DDR2_A4
A13
A_DDR2_A5
A23
A_DDR2_A6
C12
A_DDR2_A7
B23
A_DDR2_A8
B12
A_DDR2_A9
C23
A_DDR2_A10
B22
A_DDR2_A11
A12
A_DDR2_A12
A24
A_DDR2_BA0
C24
A_DDR2_BA1
B24
A_DDR2_BA2
D24
A_DDR2_MCLK
B14
/A_DDR2_MCLK
A14
A_DDR2_CKE
D23
A_DDR2_ODT
D14
/A_DDR2_RAS
D13
/A_DDR2_CAS
D12
/A_DDR2_WE
D22
A_DDR2_DQS0
B18
A_DDR2_DQS1
C17
A_DDR2_DQM0
C18
A_DDR2_DQM1
A19
A_DDR2_DQSB0
A18
A_DDR2_DQSB1
B17
A_DDR2_DQ0
B15
A_DDR2_DQ1
A21
A_DDR2_DQ2
A15
A_DDR2_DQ3
B21
A_DDR2_DQ4
C21
A_DDR2_DQ5
C14
A_DDR2_DQ6
C20
A_DDR2_DQ7
C15
A_DDR2_DQ8
C16
A_DDR2_DQ9
C19
A_DDR2_DQ10
B16
A_DDR2_DQ11
B20
A_DDR2_DQ12
A20
A_DDR2_DQ13
A16
A_DDR2_DQ14
B19
A_DDR2_DQ15
A17
IC201
H5PS5162FFR-S6C
EAN55705501
@compC
J2
VREF
J8
CK
H2
VSSQ2
B7
UDQS
N8
A4
P8
A8
L1
NC4
L2
BA0
R8
NC3
K7
RAS
F8
VSSQ3
F3
LDM
P3
A9
M3
A1
N3
A5
K8
CK
R3
NC5
L3
BA1
J7
VSSDL
L7
CAS
F2
VSSQ4
B3
UDM
M2
A10/AP
K2
CKE
R7
NC6
M7
A2
N7
A6
M8
A0
J1
VDDL
K3
WE
E8
LDQS
P7
A11
K9
ODT
A2
NC1
N2
A3
P2
A7
H8
VSSQ1
F7
LDQS
A8
UDQS
R2
A12
L8
CS
E2
NC2
E7
VSSQ5
D8
VSSQ6
D2
VSSQ7
A7
VSSQ8
B8
VSSQ9
B2
VSSQ10
P9
VSS1
N1
VSS2
J3
VSS3
E3
VSS4
A3
VSS5
G9
VDDQ1
G7
VDDQ2
G3
VDDQ3
G1
VDDQ4
E9
VDDQ5
C9
VDDQ6
C7
VDDQ7
C3
VDDQ8
C1
VDDQ9
A9
VDDQ10
R1
VDD1
M9
VDD2
J9
VDD3
E1
VDD4
A1
VDD5
B9
DQ15
B1
DQ14
D9
DQ13
D1
DQ12
D3
DQ11
D7
DQ10
C2
DQ9
C8
DQ8
F9
DQ7
F1
DQ6
H9
DQ5
H1
DQ4
H3
DQ3
H7
DQ2
G2
DQ1
G8
DQ0
IC200
H5PS5162FFR-S6C
@compC
EAN55705501
J2
VREF
J8
CK
H2
VSSQ2
B7
UDQS
N8
A4
P8
A8
L1
NC4
L2
BA0
R8
NC3
K7
RAS
F8
VSSQ3
F3
LDM
P3
A9
M3
A1
N3
A5
K8
CK
R3
NC5
L3
BA1
J7
VSSDL
L7
CAS
F2
VSSQ4
B3
UDM
M2
A10/AP
K2
CKE
R7
NC6
M7
A2
N7
A6
M8
A0
J1
VDDL
K3
WE
E8
LDQS
P7
A11
K9
ODT
A2
NC1
N2
A3
P2
A7
H8
VSSQ1
F7
LDQS
A8
UDQS
R2
A12
L8
CS
E2
NC2
E7
VSSQ5
D8
VSSQ6
D2
VSSQ7
A7
VSSQ8
B8
VSSQ9
B2
VSSQ10
P9
VSS1
N1
VSS2
J3
VSS3
E3
VSS4
A3
VSS5
G9
VDDQ1
G7
VDDQ2
G3
VDDQ3
G1
VDDQ4
E9
VDDQ5
C9
VDDQ6
C7
VDDQ7
C3
VDDQ8
C1
VDDQ9
A9
VDDQ10
R1
VDD1
M9
VDD2
J9
VDD3
E1
VDD4
A1
VDD5
B9
DQ15
B1
DQ14
D9
DQ13
D1
DQ12
D3
DQ11
D7
DQ10
C2
DQ9
C8
DQ8
F9
DQ7
F1
DQ6
H9
DQ5
H1
DQ4
H3
DQ3
H7
DQ2
G2
DQ1
G8
DQ0
MAIN DDR2
6     12
BCM (JUNO)
DDR2 1.8V By CAP - Place these Caps near Memory
HONG YEON HYUK
09.02.04
[E1]
[D1]
[L9]
[N5]
[N4]
[N12]
[N13]
THE    SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE    SYMBOL MARK OF THE SCHEMETIC.
URSA_A[1]
URSA_DQ[27]
URSA_DQ[26]
URSA_DQ[16]
URSA_DQ[31]
URSA_DQ[13]
URSA_C3M
URSA_DQ[8]
URSA_C0P
URSA_DQ[21]
URSA_A[6]
URSA_A[9]
URSA_D1P
URSA_DQ[14]
URSA_DQ[11]
URSA_A1M
URSA_DQ[29]
URSA_C2P
URSA_BCKM
URSA_C1P
URSA_A2P
URSA_A1P
URSA_DQ[9]
URSA_B3M
URSA_A[3]
URSA_D0M
URSA_B0P
URSA_D3P
URSA_C4M
URSA_C1M
URSA_C3P
URSA_B4P
URSA_DQ[0-31]
URSA_A[5]
URSA_ACKP
URSA_A[7]
URSA_A[12]
URSA_DQ[5]
URSA_DQ[18]
URSA_DQ[1]
URSA_DCKM
URSA_A0P
URSA_A[0]
URSA_A4P
URSA_D0P
URSA_A[8]
URSA_B4M
URSA_DQ[22]
URSA_B2P
URSA_A[2]
URSA_A2M
URSA_A3P
URSA_DQ[2]
URSA_DQ[28]
URSA_DCKP
URSA_C2M
URSA_C4P
URSA_DQ[17]
URSA_ACKM
URSA_A3M
URSA_DQ[12]
URSA_B1M
URSA_DQ[10]
URSA_DQ[4]
URSA_DQ[3]
URSA_DQ[7]
URSA_B3P
URSA_DQ[19]
URSA_A4M
URSA_DQ[30]
URSA_D2M
URSA_CCKM
URSA_A[11]
URSA_DQ[24]
URSA_B0M
URSA_D1M
URSA_BCKP
URSA_A0M
URSA_D4P
URSA_DQ[15]
URSA_DQ[20]
URSA_B2M
URSA_DQ[25]
URSA_A[10]
URSA_D3M
URSA_A[4]
URSA_C0M
URSA_CCKP
URSA_D2P
URSA_D4M
URSA_DQ[6]
URSA_DQ[23]
URSA_DQ[0]
URSA_C0P
URSA_C0M
URSA_C1P
URSA_C1M
URSA_C2P
URSA_C2M
URSA_CCKP
URSA_CCKM
URSA_C3P
URSA_C3M
URSA_C4P
URSA_C4M
URSA_D0P
URSA_D0M
URSA_D1P
URSA_D1M
URSA_D2P
URSA_D2M
URSA_DCKP
URSA_DCKM
URSA_D3P
URSA_D3M
URSA_D4P
URSA_D4M
URSA_B4M
URSA_B4P
URSA_B3M
URSA_B3P
URSA_BCKM
URSA_BCKP
URSA_B2M
URSA_B2P
URSA_B1M
URSA_B1P
URSA_B0M
URSA_B0P
URSA_A4M
URSA_A4P
URSA_A3M
URSA_A3P
URSA_ACKM
URSA_ACKP
URSA_A2M
URSA_A2P
URSA_A1M
URSA_A1P
URSA_A0M
URSA_A0P
URSA_B1P
C
7
3
3
0.1uF
URSA_DQ[0-31]
C745
10uF
C719
0.1uF
M_SPI_CK
MEMC_RXE4+
URSA_A[0-12]
R720
100
R722
100
C
7
3
0
0.1uF
C
7
4
1
0
.
1
u
F
C
7
3
1
0.1uF
R701
2.2K
C715
0.1uF
MEMC_RXOC-
C700
15pF
M_XTALI
R712
100
C
7
4
0
0
.
1
u
F
URSA_DQM3
MEMC_RXO0+
MEMC_RESET
C724
0.1uF
+3.3V_MEMC
URSA_BA1
MEMC_RXO2-
R721
100
L703
BLM18PG121SN1D
R727
100
C712
0.1uF
MEMC_RXE2+
+5V
R737
1K
URSA_BA0
C739
1uF
C726
0.1uF
C706
0.1uF
L700
BLM18PG121SN1D
C720
0.1uF
R703
56
R723
100
MEMC_SDA
R732
10K
C
7
2
8
0
.
1
u
F
MEMC_RXEC+
R707
56
+3.3V_MEMC
R702
56
MEMC_RXO1+
M_SPI_DI
+3.3V_MEMC
R715
10K
L706
BLM18PG121SN1D
C743
0.1uF
C707
22uF
16V
URSA_DQSB2
URSA_MCLK
+3.3V_ST
M_SPI_DO
R704
10K
C722
10uF
10V
MEMC_RXE3-
C
7
1
4
0
.
1
u
F
M_XTALI
R728
0
MEMC_RXO2+
C708
10uF
URSA_DQS0
C723
0.1uF
C
7
0
4
0
.
1
u
F
+1.26V_MEMC
URSA_DQS1
C749
0.1uF
MEMC_RXO3-
ISP_TXD_MEMC
J23
C705
0.1uF
R718
100
C
7
3
7
0
.
1
u
F
M_SPI_DO
MEMC_RXO4+
R706
56
MEMC_RXEC-
L701
BLM18PG121SN1D
C716
0.1uF
C721
0.1uF
C
7
0
3
0
.
1
u
F
L705
BLM18PG121SN1D
URSA_MCLKE
C748
0.1uF
C
7
2
9
0
.
1
u
F
C
7
3
5
0
.
1
u
F
R708
1K
URSA_MCLKZ1
R700
2.2K
MEMC_RXE4-
R717
100
+3.3V_MEMC
+3.3V_MEMC
C709
22uF
16V
R714
10K
X700
12MHz
URSA_MCLKZ
MEMC_RXO3+
URSA_CASZ
URSA_ODT
R716
100
R741
1K
C713
10uF
C717
1uF
C746
0.1uF
C
7
3
4
0.1uF
MEMC_RXE0+
+3.3V_MEMC
C711
10uF
R705
1M
C747
0.1uF
MEMC_RXE3+
+3.3V_MEMC
R742
1K
OPT
C
7
3
8
0
.
1
u
F
M_SPI_CK
C
7
3
2
0.1uF
R724
100
ISP_RXD_MEMC
J23
MEMC_RXE1-
MEMC_RXE0-
C725
10uF
URSA_DQSB1
M_SPI_CZ
R709
1K
OPT
MEMC_RXO0-
URSA_MCLK1
MEMC_RXE1+
C727
0.1uF
R711
0
C702
10uF
URSA_DQM2
ISP_RXD_MEMC
C
7
3
6
0
.
1
u
F
URSA_DQM0
+1.8V_MEMC
URSA_DQSB0
MEMC_RXO4-
MEMC_RXO1-
M_XTALO
URSA_WEZ
P700
TJC2508-4A
ISP_FRC
1
2
3
4
C710
10uF
R738
1K
OPT
MEMC_SCL
R725
100
URSA_DQS2
R729
820
URSA_DQM1
L704
BLM18PG121SN1D
M_SPI_DI
MEMC_RXOC+
R719
100
C
7
4
2
0
.
1
u
F
M_XTALO
R710
0
R726
100
M_SPI_CZ
MEMC_RXE2-
URSA_DQS3
IC700
W25X20AVSNIG
EAN50547501
3
WP
2
DO
4
GND
1
CS
5
DIO
6
CLK
7
HOLD
8
VCC
C701
15pF
C718
0.1uF
+3.3V_MEMC
R713
100
URSA_RASZ
L702
BLM18PG121SN1D
URSA_DQSB3
ISP_TXD_MEMC
12V_TCON
LVDS_SEL
9:AO33;M21
PWM_DIM
9:AD15;4:D19
OPC_OUT1
4:D18
OPC_EN
9:AO32
OPC_OUT2
4:E21
L707
CB3216PA501E
LVDS_SEL
9:AO33;AL17
C757
0.1uF
16V
C756
0.1uF
16V
C755
0.1uF
16V
C754
0.1uF
16V
BIT_SEL
R730
0
OPT
C752
0.1uF
OPT
C753
1000pF
50V
C751
22uF
25V
C744
10uF
10V
C750
10uF
C758
0.1uF
R743
1K
OPT
R731
1K
OPT
+3.3V_MEMC
R744
1K
R740
1K
IC701
LGE7329A
EAN60659201
E1
SDAS
D1
SCLS
F1
GPIO[8]
G1
GPIO[9]
K8
GND_14
E5
VDDC_1
E2
GPIO[10]
F2
GPIO[11]
F3
GPIO[12]
G2
GPIO[13]
M4
GPIO[22]
M5
GPIO[23]
G3
GPIO[14]
E4
GPIO[15]
F4
GPIO[16]
G4
GPIO[17]
H4
GPIO[18]
J4
GPIO[19]
K4
GPIO[20]
L4
GPIO[21]
J6
VDDP_2
H9
GND_7
F6
VDDC_2
H1
MDATA[20]
H2
MDATA[19]
H3
MDATA[17]
J1
MDATA[22]
J2
MDATA[27]
J3
MDATA[28]
K1
MDATA[25]
K2
MDATA[30]
K6
AVDD_DDR_2
K3
DQM[3]
L1
DQM[2]
J8
GND_10
L2
DQS[2]
L3
DQSB[2]
L6
AVDD_DDR_4
L8
VDDP_3
H10
GND_8
M1
DQS[3]
M2
DQSB[3]
L7
AVDD_DDR_5
M3
MDATA[31]
N1
MDATA[24]
J9
GND_11
N2
MDATA[26]
N3
MDATA[29]
L10
AVDD_DDR_6
P1
MDATA[23]
R1
MDATA[16]
T1
MDATA[18]
T2
MDATA[21]
R2
MCLK[0]
P2
MCLKZ[0]
G7
GND_1
L9
AVDD_MEMPLL
N5
MVREF
N4
ODT
T3
RASZ
R3
CASZ
P3
MADR[0]
T4
MADR[2]
R4
MADR[4]
J10
GND_12
P4
MADR[6]
T5
MADR[8]
R5
MADR[11]
P5
WEZ
T6
BADR[1]
R6
BADR[0]
P6
MADR[1]
T7
MADR[10]
L11
AVDD_DDR_7
R7
MADR[5]
P7
MADR[9]
T8
MADR[12]
R8
MADR[7]
P8
MADR[3]
N8
MCLKE
K10
GND_16
F7
VDDC_3
T9
MDATA[4]
R9
MDATA[3]
K7
GND_13
P9
MDATA[1]
T10
MDATA[6]
K11
AVDD_DDR_3
R10
MDATA[11]
P10
MDATA[12]
T11
MDATA[9]
R11
MDATA[14]
J11
AVDD_DDR_1
P11
DQM[1]
T12
DQM[0]
R12
DQS[0]
P12
DQSB[0]
H11
VDDP_1
T13
DQS[1]
R13
DQSB[1]
P13
MDATA[15]
T14
MDATA[8]
R14
MDATA[10]
P14
MDATA[13]
T15
MDATA[7]
R15
MDATA[0]
P15
MDATA[2]
T16
MDATA[5]
R16
MCLK[1]
P16
MCLKZ[1]
N9
GPIO[26]
N10
GPIO[27]
N11
GND_17
M11
RESET
G6
VDDC_4
N12
GPIO[28]
N13
GPIO[29]
N14
GPIO[30]
L13
SCK
M13
SDI
M12
SDO
K13
CSZ
L12
PWM1
K12
PWM0
J13
GPIO[0]
H13
GPIO[1]
G13
GPIO[2]
F13
GPIO[3]
E13
GPIO[4]
F12
GPIO[5]
D14
GPIO[6]
E12
GPIO[7]
N6
GPIO[24]
H6
VDDC_5
N15
LVD4M
N16
LVD4P
M14
LVD3M
M15
LVD3P
F8
AVDD_33_1
M16
LVDCKM
L16
LVDCKP
L15
LVD2M
L14
LVD2P
G9
GND_3
K14
LVD1M
J14
LVD1P
J16
LVD0M
J15
LVD0P
H15
LVC4M
H16
LVC4P
H14
LVC3M
G14
LVC3P
G16
LVCCKM
G15
LVCCKP
F15
LVC2M
F16
LVC2P
F14
LVC1M
E14
LVC1P
E16
LVC0M
E15
LVC0P
G10
GND_4
F9
AVDD_33_2
D16
LVB4M
D15
LVB4P
C16
LVB3M
B16
LVB3P
A16
LVBCKM
A15
LVBCKP
B15
LVB2M
C15
LVB2P
D2
GPIO_3
E3
GPIO_10
E10
GPIO_11
D10
GPIO_7
D8
GPIO_5
D12
REXT
C14
LVB1M
C13
LVB1P
A13
LVB0M
B13
LVB0P
D7
GPIO_4
D9
GPIO_6
B12
LVA4M
A12
LVA4P
C12
LVA3M
C11
LVA3P
A11
LVACKM
B11
LVACKP
B10
LVA2M
A10
LVA2P
C10
LVA1M
C9
LVA1P
A9
LVA0M
B9
LVA0P
F10
AVDD_PLL
G8
GND_2
D11
GPIO_8
D13
GPIO_9
E11
GPIO_12
N7
GPIO[25]
D6
SCLM
D5
SDAM
A14
GPIO_1
B14
GPIO_2
D3
XIN
D4
XOUT
K16
GPIO_14
K15
GPIO_13
H7
GND_5
G11
AVDD_LVDS_2
B8
RO0N
A8
RO0P
C8
RO1N
C7
RO1P
A7
RO2N
B7
RO2P
B6
ROCKN
A6
ROCKP
C6
RO3N
C5
RO3P
A5
RO4N
B5
RO4P
H8
GND_6
F11
AVDD_LVDS_1
B4
RE0N
A4
RE0P
C4
RE1N
C3
RE1P
A3
RE2N
B3
RE2P
B2
RECKN
A2
RECKP
C2
RE3N
C1
RE3P
A1
RE4N
B1
RE4P
GND_9
J7
GND_15 K9
P702
TF05-51S
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
P701
TF05-41S
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
MDS61887701
GAS2
GAS2
MDS61887701
GAS5
GAS5
MDS61887701
GAS3
GAS3
MDS61887701
GAS4
GAS4
Only use for 42Inch
MDS61887701
GAS1
GAS1
R735
0
OPC_EN
R747
OPT
0
R739
0
OPC_EN
R733
0
OPC_EN
R736
0
R758
0
OPT
R734
0
OPT
R748
0
+3.3V_MEMC
R745
0
OPT
R746
4.7K OPT
7       12
JUNO
LOW
ISP Port for MEMC
HIGH
I2C
HIGH
SPI
EEPROM
HIGH
HIGH
SPI FLASH
PWM1
LOW
PWM0
HIGH
HIGH
GPIO8
HIGH
XTAL
PI Result
PI Result
09.02.04.
KIM SUNG KYEONG(FRC)
PARK SUNG WON(LVDS)
LVDS / FRC
                    GPIO12  GPIO14
Non M+S LVDS         LOW     LOW
M+S 42" Mini LVDS    LOW     HIGH
M+S 47" Mini LVDS    HIGH    LOW
M+S 37" Mini LVDS    HIGH    HIGH
for FRC one-board
SMD Gasket Option
1
2
3
4
5
PCB BACK VIEW
THE    SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE    SYMBOL MARK OF THE SCHEMETIC.
DDR_DQ[3]
URSA_A[9]
DDR_DQ[15]
URSA_DQ[20]
DDR_DQ[6]
DDR_DQ[22]
DDR_DQ[12]
DDR_DQ[28]
DDRA_A[6]
DDR_DQ[25]
DDRB_A[1]
URSA_DQ[31]
DDR_DQ[15]
DDR_DQ[26]
DDRB_A[11]
DDR_DQ[19]
DDRA_A[9]
DDR_DQ[1]
DDR_DQ[10]
URSA_DQ[22]
DDRB_A[0-12]
DDRB_A[6]
DDR_DQ[13]
URSA_DQ[8]
URSA_DQ[18]
DDRA_A[3]
URSA_DQ[30]
DDR_DQ[11]
URSA_DQ[25]
DDR_DQ[17]
URSA_DQ[12]
DDR_DQ[23]
DDRA_A[4]
DDR_DQ[14]
DDR_DQ[20]
URSA_A[3]
DDRB_A[10]
DDR_DQ[3]
URSA_DQ[17]
DDRB_A[11]
DDRA_A[7]
DDRB_A[5]
DDRA_A[0]
URSA_DQ[9]
DDRA_A[0-12]
DDR_DQ[31]
URSA_A[4]
DDR_DQ[20]
DDRA_A[6]
URSA_A[8]
DDRB_A[0]
URSA_DQ[16]
URSA_DQ[13]
URSA_A[1]
URSA_A[5]
URSA_DQ[23]
URSA_A[10]
DDR_DQ[5]
DDRA_A[4]
DDR_DQ[19]
DDR_DQ[7]
DDRA_A[5]
DDRB_A[1]
URSA_DQ[1]
DDR_DQ[2]
URSA_A[6]
DDR_DQ[23]
DDR_DQ[0-15]
DDRA_A[12]
URSA_A[11]
URSA_A[8]
DDR_DQ[26]
DDR_DQ[22]
URSA_A[1]
URSA_DQ[4]
URSA_DQ[26]
URSA_DQ[7]
DDRB_A[7]
DDRB_A[9]
DDR_DQ[29]
DDR_DQ[17]
URSA_DQ[14]
URSA_A[6]
DDR_DQ[30]
DDR_DQ[27]
URSA_DQ[6]
DDRA_A[5]
DDRA_A[1]
DDR_DQ[21]
DDR_DQ[4]
DDRA_A[12]
DDR_DQ[14]
DDR_DQ[0]
DDR_DQ[27]
DDRA_A[0]
DDRA_A[3]
DDRB_A[6]
URSA_A[2]
DDR_DQ[16]
DDR_DQ[24]
URSA_A[7]
DDRA_A[2]
URSA_DQ[10]
URSA_DQ[24]
DDR_DQ[31]
URSA_DQ[27]
DDRB_A[7]
DDR_DQ[13]
DDR_DQ[4]
URSA_A[12]
URSA_DQ[11]
DDRB_A[2]
DDR_DQ[24]
URSA_A[3]
URSA_DQ[5]
DDRB_A[10]
DDRA_A[11]
DDRB_A[8]
DDR_DQ[11]
URSA_A[4]
DDR_DQ[21]
URSA_A[0]
URSA_DQ[0]
DDR_DQ[7]
DDR_DQ[12]
DDRB_A[5]
DDR_DQ[1]
DDR_DQ[9]
DDR_DQ[30]
URSA_DQ[21]
URSA_A[5]
DDR_DQ[16]
DDR_DQ[29]
URSA_DQ[2]
URSA_DQ[28]
URSA_DQ[3]
DDRB_A[12]
URSA_A[7]
DDR_DQ[5]
DDRA_A[10]
DDR_DQ[18]
DDR_DQ[9]
DDRB_A[3]
DDRB_A[2]
URSA_DQ[15]
DDR_DQ[0]
URSA_DQ[29]
DDRB_A[0]
DDR_DQ[8]
DDRA_A[8]
DDR_DQ[2]
URSA_A[12]
DDRA_A[10]
DDRA_A[11]
DDRB_A[4]
DDRB_A[3]
DDRA_A[2]
URSA_DQ[19]
DDRA_A[9]
DDR_DQ[8]
DDR_DQ[25]
DDRA_A[1]
DDR_DQ[18]
URSA_A[2]
DDR_DQ[16-31]
DDRB_A[4]
URSA_A[9]
DDR_DQ[28]
DDRA_A[8]
DDRA_A[7]
URSA_A[11]
DDRB_A[12]
DDRB_A[9]
DDRB_A[8]
URSA_A[10]
DDR_DQ[10]
URSA_A[0]
DDR_DQ[6]
C837
0.1uF
URSA_MCLKE
7:T4;T8
+1.8V_FRC_DDR
C805
0.1uF
R818
56
C827
0.1uF
R802
1K
1%
C809
0.1uF
URSA_BA0
7:R4;U10
URSA_DQS3
7:I13
A_URSA_CASZ
X15
URSA_RASZ
+1.8V_MEMC
URSA_RASZ
AR816
56
URSA_MCLK
7:I11
R811
56
C818
0.1uF
B_URSA_BA0
AR804
22
URSA_DQS2
7:I14
A_URSA_CASZ
C838
0.1uF
A_URSA_WEZ
U8
A_URSA_BA0
AA15
C824
0.1uF
AR811
22
C807
0.1uF
C831
0.1uF
R807
56
C808
1000pF
C802
10uF
R816
56
R822
1K
1%
AR808
22
L800
BLM18PG121SN1D
AR802
56
URSA_A[0-12]
R804
22
URSA_ODT
7:I10;Q13
C836
0.1uF
+1.8V_FRC_DDR
R823
150
OPT
AR814
56
+1.8V_FRC_DDR
AR800
56
C819
0.1uF
A_URSA_RASZ
R810
56
B_URSA_BA0
AR817
56
URSA_BA1
7:R4;U10
+1.8V_FRC_DDR
+1.8V_FRC_DDR
C829
0.1uF
A_URSA_BA1
URSA_DQ[0-31]
7:AB4;AL20
URSA_CASZ
C825
0.1uF
URSA_DQM1
7:W4
URSA_DQS1
7:Y4
C813
10uF
R819
56
R815
56
A_URSA_MCLKE
U8
URSA_MCLKZ1
7:AB4
R806
56
URSA_ODT
7:I10;X13
R801
1K
1%
C801
10uF
10V
C832
1000pF
R805
22
URSA_CASZ
C835
0.1uF
URSA_BA0
7:R4;T9
URSA_DQSB3
7:I13
C812
0.1uF
C810
0.1uF
C800
0.1uF
C823
10uF
B_URSA_MCLKE
T9
B_URSA_BA1
AR812
22
R803
22
AR807
22
AR813
22
C820
0.1uF
B_URSA_CASZ
R15
C815
0.1uF
B_URSA_WEZ
Q12
AR810
22
AR815
56
C839
0.1uF
B_URSA_RASZ
R15
C841
0.1uF
R820
56
R813
22
URSA_WEZ
7:R4;T8
C816
0.1uF
URSA_DQM2
7:I15
+1.8V_FRC_DDR
AR809
22
B_URSA_RASZ
C806
0.1uF
C826
0.1uF
AR801
56
URSA_MCLKE
7:T4;U9
R812
22
A_URSA_BA0
URSA_DQSB2
7:I14
URSA_DQM3
7:I15
C840
0.1uF
C834
0.1uF
A_URSA_RASZ
X15
URSA_DQ[0-31]
7:AB4;D20
B_URSA_WEZ
T9
C833
0.1uF
A_URSA_BA1
AA15
C814
0.1uF
URSA_MCLKZ
7:I10
C821
0.1uF
C817
0.1uF
R800
150
OPT
R808
56
B_URSA_CASZ
AR806
22
B_URSA_BA1
URSA_DQS0
7:X4
C822
10uF
10V
C804
0.1uF
C803
0.1uF
B_URSA_MCLKE
Q14
URSA_WEZ
7:R4;U9
URSA_MCLK1
7:AA4
R814
22
R817
56
C811
0.1uF
R821
1K
1%
R809
56
+1.8V_FRC_DDR
URSA_DQSB0
7:X4
A_URSA_MCLKE
Z14
AR803
56
C828
10uF
URSA_BA1
7:R4;T8
C830
0.1uF
URSA_DQM0
7:W4
URSA_DQSB1
7:Y4
AR805
22
A_URSA_WEZ
X12
C844
0.1uF
C842
0.1uF
C843
0.1uF
+1.8V_FRC_DDR
+1.8V_FRC_DDR
C850
0.1uF
C848
0.1uF
C852
0.1uF
C845
0.1uF
+1.8V_FRC_DDR
C846
0.1uF
C851
0.1uF
+1.8V_MEMC
C849
0.1uF
C847
0.1uF
IC801
H5PS5162FFR-S6C
EAN55705501
J2
VREF
J8
CK
H2
VSSQ2
B7
UDQS
N8
A4
P8
A8
L1
NC4
L2
BA0
R8
NC3
K7
RAS
F8
VSSQ3
F3
LDM
P3
A9
M3
A1
N3
A5
K8
CK
R3
NC5
L3
BA1
J7
VSSDL
L7
CAS
F2
VSSQ4
B3
UDM
M2
A10/AP
K2
CKE
R7
NC6
M7
A2
N7
A6
M8
A0
J1
VDDL
K3
WE
E8
LDQS
P7
A11
K9
ODT
A2
NC1
N2
A3
P2
A7
H8
VSSQ1
F7
LDQS
A8
UDQS
R2
A12
L8
CS
E2
NC2
E7
VSSQ5
D8
VSSQ6
D2
VSSQ7
A7
VSSQ8
B8
VSSQ9
B2
VSSQ10
P9
VSS1
N1
VSS2
J3
VSS3
E3
VSS4
A3
VSS5
G9
VDDQ1
G7
VDDQ2
G3
VDDQ3
G1
VDDQ4
E9
VDDQ5
C9
VDDQ6
C7
VDDQ7
C3
VDDQ8
C1
VDDQ9
A9
VDDQ10
R1
VDD1
M9
VDD2
J9
VDD3
E1
VDD4
A1
VDD5
B9
DQ15
B1
DQ14
D9
DQ13
D1
DQ12
D3
DQ11
D7
DQ10
C2
DQ9
C8
DQ8
F9
DQ7
F1
DQ6
H9
DQ5
H1
DQ4
H3
DQ3
H7
DQ2
G2
DQ1
G8
DQ0
IC800
H5PS5162FFR-S6C
EAN55705501
J2
VREF
J8
CK
H2
VSSQ2
B7
UDQS
N8
A4
P8
A8
L1
NC4
L2
BA0
R8
NC3
K7
RAS
F8
VSSQ3
F3
LDM
P3
A9
M3
A1
N3
A5
K8
CK
R3
NC5
L3
BA1
J7
VSSDL
L7
CAS
F2
VSSQ4
B3
UDM
M2
A10/AP
K2
CKE
R7
NC6
M7
A2
N7
A6
M8
A0
J1
VDDL
K3
WE
E8
LDQS
P7
A11
K9
ODT
A2
NC1
N2
A3
P2
A7
H8
VSSQ1
F7
LDQS
A8
UDQS
R2
A12
L8
CS
E2
NC2
E7
VSSQ5
D8
VSSQ6
D2
VSSQ7
A7
VSSQ8
B8
VSSQ9
B2
VSSQ10
P9
VSS1
N1
VSS2
J3
VSS3
E3
VSS4
A3
VSS5
G9
VDDQ1
G7
VDDQ2
G3
VDDQ3
G1
VDDQ4
E9
VDDQ5
C9
VDDQ6
C7
VDDQ7
C3
VDDQ8
C1
VDDQ9
A9
VDDQ10
R1
VDD1
M9
VDD2
J9
VDD3
E1
VDD4
A1
VDD5
B9
DQ15
B1
DQ14
D9
DQ13
D1
DQ12
D3
DQ11
D7
DQ10
C2
DQ9
C8
DQ8
F9
DQ7
F1
DQ6
H9
DQ5
H1
DQ4
H3
DQ3
H7
DQ2
G2
DQ1
G8
DQ0
MST7323S DDR2
8      12
MSTAR (JUNO)
DDR2 1.8V By CAP - Place these Caps near Memory
PI Result
FRC DDR2
HONG YEON HYUK
09.02.04
 resonance Compensation
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