DOWNLOAD LG 42SL90-UA (CHASSIS:LA92S) Service Manual ↓ Size: 5.7 MB | Pages: 44 in PDF or view online for FREE

Model
42SL90-UA (CHASSIS:LA92S)
Pages
44
Size
5.7 MB
Type
PDF
Document
Service Manual
Brand
Device
TV / LCD
File
42sl90-ua-chassis-la92s.pdf
Date
PREV: LG 42SL90QR-MA (CHASSIS:LP91L) Service Manual

LG 42SL90-UA (CHASSIS:LA92S) Service Manual ▷ View online

THE    SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE    SYMBOL MARK OF THE SCHEMETIC.
TUNER
5    10
SL90
09/08/24
TS_DATA[2]
TS_DATA[1]
TS_DATA[7]
TS_DATA[5]
TS_DATA[6]
TS_DATA[0-7]
@netLa
TS_DATA[3]
TS_DATA[4]
TS_DATA[0]
R516
4.7K
TU500-*1
UCA36AL
Tuner-Sanyo
14
IF_AGC
13
D_IF2
5
NC_3[RF_AGC]
12
D_IF1
11
NC_5
2
NC_2
19
VIDEO
18
NC_7
10
AS
4
+5V[MAIN]
1
NC_1
17
NC_6[AFT]
9
SCL
8
SDA
3
GND_1
16
SIF
7
GND_2
6
NC_4[VT]
15
+5V[VIF]
20
SHIELD
C531
0.1uF
50V
C551
0.1uF
50V
C550
100uF
16V
+5V_TU
C535
0.1uF
50V
+5V_EXT
C552
1uF
10V
C528
36pF
50V
OPT
R546 OPT
C512
0.047uF
50V
OPT
L509
MLB-201209-0120P-N2
R523-*1
0
IF_Short
VSB_RESET
R501
0
C500
0.1uF
16V
R548
22
R528
100
+1.2V_DVDD_PVSB
JP500
C539
0.1uF
50V
C525
0.1uF
50V
IF_P
C504
0.01uF
25V
L511
500
OPT
+3.3V_AVDD_PVSB
C534
10uF
16V
3216
+12V
C555
100uF
16V
R549
20K
R541
100
OPT
AR500
100
1/16W
R532 OPT
IF_AGC
C502
0.1uF
16V
C538
0.1uF
R512
4.7K
C540
0.1uF
50V
R502
100
OPT
+3.3V_AVDD_PVSB
R506
22
R539
1M
C548
27pF
50V
C520
27pF
50V
OPT
+3.3V_AVDD_PVSB
C521
0.1uF
C544
0.1uF
50V
C507
100pF
50V
C553
OPT
C543
0.1uF
50V
IC504
SC156515M-1.8TR
2
VIN
1
EN
3
GND
5
ADJ
4
VO
R545
OPT
R534
5.1K
OPT
C546
27pF
50V
JP502
C524
0.01uF
25V
IC500
AS7809DTRE1
2
GND
3
OUTPUT
1
INPUT
R533 OPT
C532
10uF
16V
3216
C542
0.01uF
C537
0.1uF
50V
R527
100
C519
47uF
16V
TS_CLK
+3.3V_PVSB
+1.2V_PVSB
R538
20K
R540
4.7K
R535
470
PV
C508
0.1uF
50V
R524
220nH
IF_LC_Filter
+3.3V_DVDD_PVSB
Q501
ISA1530AC1
E
B
C
L510
CB3216PA501E
TS_VALID
R510
0
OPT
+5V_TU
FE_DEMOD_SCL
+3.3V_PVSB
IC502
LGDT3305
1
NC_1
2
VINA2
3
VINA1
4
INCAP
5
VSSAAD10A
6
I2CSEL
7
ANTCON
8
VDD_1
9
I2CRPT_SCL
10
I2CRPT_SDA
11
IFOUT
12
RFOUT
13
TPERR
14
VDD33_1
15
TPVALID
16
TPDATA[0]
17
VSS33_1
18
TPDATA[1]
19
TPDATA[2]
20
TPDATA[3]
21
TPDATA[4]
22
TPDATA[5]
23
TPDATA[6]
24
TPDATA[7]
25
TPCLK
26
TPSOP
27
NIRQ
28
SDA
29
VDD33_2
30
SCL
31
VSS_1
32
VDD_2
33
VSS_2
34
VSS33_2
35
PLLAVDD
36
PLLAVSS
37NRST
38OPM
39VDD33_3
40NC_2
41VSS33_3
42XTALI
43XTALO
44VSS_3
45XM
46VDD_3
47VSSDAD10
48VCCAAD10A
JP501
X500
25MHz
+3.3V_FE
VSB_CTRL
R519
0
R505
22
L507
CB3216PA501E
FE_TUNER_SDA
POWER_EN
006:AR30;004:X20;004:AL8;004:AN20
R500
0
OPT
Q500
ISA1530AC1
E
B
C
C558
0.1uF
50V
C513
0.01uF
50V
C556
100uF
16V
C505
0.33uF
16V
LD500
PV
FE_VMAIN
006:C23
C527
36pF
50V
OPT
VCOMO
006:C23
R542
0
OPT
C533
0.1uF
+1.2V_PVSB
IC503
SC4215ISTRT
3
VIN
2
EN
4
NC_2
1
NC_1
5
NC_3
6
VO
7
ADJ
8
GND
R508
10K
IC501
KIA78R05F
1
VIN
2
VC
3
VOUT
4
NC
5
GND1
6
GND2
L502
CM2012F6R8KT
6.8uH
IF_P
R531
0
R515
270
FE_TUNER_SCL
+5V_TU
C506
0.1uF
50V
AR501
100
C554
OPT
R530
100
R511
0
C557
0.1uF
50V
C514
10uF
10V
L506
270nH
R552
8.2K
IF_N
C526
82pF
50V
TU500
TDVW-H103F
Tuner-LGIT
14
IF_AGC
13
DIF[-]
5
RF_AGC
12
DIF[+]
11
NC_3
NC_2
2
19
VIDEO
18
AUDIO
10
AS
4
+B1
NC_1
1
17
NC_4
9
CLOCK
8
DATA
3
GND_1
16
SIF
7
GND_2
6
NC[VT]
15
+B2
20
SHIELD
TS_DATA[0-7]
+3.3V_DVDD_PVSB
GND
AR502
100
C511
0.1uF
16V
OPT
C536
0.1uF
+3.3V_DVDD_PVSB
+3.3V_PVSB
R551
15K
C541
0.01uF
R520
0
C530
10uF
16V
3216
R526
1K
C547
2.2uF
16V
L508
500
R514
270
IF_AGC
C510
100pF
50V
R547
22
L500
BG2012B800
IF_N
R509
OPT
C545
2.2uF
16V
C501
100uF
16V
R525
0
1/4W
5%
+5V_TU
R524-*1
0
IF_Short
R513
470
R504
2.2K
OPT
R529
1K
C523
27pF
50V
OPT
FE_TUNER_SDA
TS_VALID
L503
CM3216F100KE
10uH
R550
10K
C503
100uF
16V
FE_TUNER_SCL
TS_SYNC
TS_SYNC
R517
0
TS_CLK
R518
0
+1.2V_DVDD_PVSB
C516
0.1uF
50V
OPT
R507
12K
FE_DEMOD_SDA
FE_SIF
006:V30
C549
1uF
16V
+5V_TU
R544
47K
D500
1N4148W
R523
220nH
IF_LC_Filter
R503
10K
OPT
R543
1K
C529
47pF
C517
100uF
16V
C522
100uF
16V
VSB +3.3V B+ BLOCK
VSS33
PLLAVDD
The value of coil & cap’ could be changed to optimized each
MStar Application
VSB +1.0V B+ BLOCK
TPDATA[0]
VDD
Option for FM Rejection
TPVALID
VSS33
R2
JTAG
SDA
R1
VDD33
TPCLK
TPDATA[7]
SCL
TPERR
VDD33
TPDATA[6]
VSS
TPDATA[5]
VROA
TPDATA[4]
ANTCON
TPDATA[3]
INCAP
TPDATA[2]
VDD
TPDATA[1]
RF OUT
XTALI
Close to tuner
VSS
VINA2
 (I2C Channel 6)
OPM
I2CSEL
NRST
SLIM_SCAN
XTALO
VSS33
VINA1
XM
VDD
I2CRPT_SCL
NIRQ
VCCAAD10A
I2CRPT_SDA
VSS
VSSAD10
IF OUT
TPSOP
MStar Application
VDD33
VSSAAD10A
PLLAVSS
V0 = 0.8(R1+R2) / R2
THE    SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE    SYMBOL MARK OF THE SCHEMETIC.
SL90
09/06/24
DDR2
7     10
BDDR2_D[13]
SDDR_D[11]
BDDR2_D[8]
TDDR_A[0-12]
BDDR2_A[4]
BDDR2_A[5]
SDDR_DQM0_P
TDDR_A[7]
TDDR_D[6]
ADDR2_A[6]
SDDR_BA[1]
SDDR_D[10]
BDDR2_A[2]
BDDR2_A[10]
SDDR_D[7]
ADDR2_D[1]
SDDR_A[9]
TDDR_D[14]
TDDR_DQS0_P
BDDR2_A[11]
BDDR2_D[2]
ADDR2_D[0]
BDDR2_D[8]
BDDR2_D[4]
BDDR2_A[12]
ADDR2_A[12]
TDDR_A[1]
TDDR_D[7]
ADDR2_D[5]
SDDR_D[8]
BDDR2_D[0]
ADDR2_D[11]
TDDR_A[1]
TDDR_A[0]
TDDR_D[2]
TDDR_A[3]
BDDR2_D[15]
ADDR2_A[7]
BDDR2_A[5]
ADDR2_A[8]
SDDR_D[14]
ADDR2_A[0]
TDDR_D[15]
TDDR_DQS1_N
TDDR_BA[1]
BDDR2_D[6]
SDDR_A[11]
ADDR2_D[10]
BDDR2_D[11]
SDDR_D[9]
TDDR_D[10]
SDDR_A[2]
SDDR_A[7]
TDDR_D[0]
SDDR_D[12]
SDDR_D[3]
TDDR_D[4]
TDDR_D[8]
SDDR_D[9]
ADDR2_D[6]
SDDR_D[5]
BDDR2_A[0-12]
ADDR2_D[5]
ADDR2_D[13]
SDDR_A[3]
SDDR_A[2]
BDDR2_D[0-15]
BDDR2_D[15]
ADDR2_D[7]
/TDDR_CAS
TDDR_DQM0_P
ADDR2_D[2]
ADDR2_D[1]
TDDR_A[10]
TDDR_MCLK
SDDR_A[4]
TDDR_D[13]
ADDR2_D[9]
SDDR_A[0]
ADDR2_A[8]
TDDR_A[11]
TDDR_D[3]
TDDR_BA[0]
BDDR2_A[9]
TDDR_D[13]
ADDR2_D[11]
BDDR2_A[9]
SDDR_D[10]
BDDR2_D[2]
ADDR2_D[10]
ADDR2_A[2]
SDDR_A[8]
TDDR_D[12]
TDDR_D[1]
TDDR_A[7]
SDDR_A[12]
ADDR2_D[3]
SDDR_A[7]
TDDR_A[3]
BDDR2_D[10]
SDDR_D[13]
TDDR_A[8]
ADDR2_A[10]
TDDR_D[11]
SDDR_D[8]
SDDR_A[11]
SDDR_D[2]
BDDR2_A[3]
ADDR2_D[0]
TDDR_DQS1_P
SDDR_A[5]
TDDR_A[2]
SDDR_D[14]
TDDR_D[8]
TDDR_A[6]
SDDR_A[10]
ADDR2_A[11]
BDDR2_D[14]
TDDR_D[12]
ADDR2_A[4]
/TDDR_WE
TDDR_D[9]
TDDR_A[4]
SDDR_D[0-15]
ADDR2_A[5]
SDDR_D[5]
ADDR2_A[9]
SDDR_DQS0_P
TDDR_D[2]
TDDR_A[0]
ADDR2_D[4]
BDDR2_A[10]
ADDR2_A[7]
SDDR_D[12]
SDDR_D[0]
BDDR2_A[8]
TDDR_A[2]
SDDR_D[2]
SDDR_D[0]
ADDR2_D[4]
TDDR_A[6]
BDDR2_D[6]
BDDR2_D[3]
BDDR2_A[4]
TDDR_D[5]
TDDR_A[4]
TDDR_CKE
BDDR2_A[1]
ADDR2_A[12]
SDDR_A[3]
SDDR_A[6]
ADDR2_D[0-15]
TDDR_D[10]
ADDR2_A[1]
TDDR_A[12]
SDDR_D[13]
SDDR_D[11]
SDDR_D[4]
TDDR_A[9]
ADDR2_A[0]
/SDDR_CAS
BDDR2_A[1]
BDDR2_D[7]
BDDR2_D[5]
SDDR_A[8]
/TDDR_MCLK
BDDR2_D[11]
SDDR_D[6]
BDDR2_A[6]
SDDR_DQS0_N
ADDR2_A[5]
ADDR2_D[14]
BDDR2_D[7]
TDDR_A[8]
ADDR2_D[15]
ADDR2_A[11]
BDDR2_A[0]
TDDR_D[0]
ADDR2_D[8]
TDDR_D[14]
BDDR2_A[8]
TDDR_D[7]
TDDR_A[10]
ADDR2_D[9]
SDDR_D[1]
SDDR_A[6]
ADDR2_A[6]
ADDR2_D[3]
BDDR2_D[5]
BDDR2_D[10]
TDDR_A[5]
TDDR_A[12]
ADDR2_A[2]
ADDR2_A[4]
BDDR2_A[7]
BDDR2_D[13]
SDDR_A[4]
ADDR2_D[8]
ADDR2_D[12]
SDDR_A[5]
TDDR_D[11]
ADDR2_MCLK
TDDR_D[9]
TDDR_D[6]
ADDR2_A[1]
SDDR_D[6]
TDDR_D[5]
SDDR_A[12]
BDDR2_D[9]
BDDR2_A[6]
BDDR2_A[7]
SDDR_D[1]
ADDR2_D[14]
ADDR2_D[12]
TDDR_D[4]
BDDR2_D[3]
SDDR_A[0-12]
BDDR2_D[0]
BDDR2_A[11]
TDDR_D[3]
SDDR_D[3]
BDDR2_D[4]
BDDR2_A[12]
BDDR2_A[0]
/SDDR_RAS
ADDR2_BA[1]
SDDR_A[10]
SDDR_D[15]
ADDR2_A[10]
TDDR_DQS0_N
SDDR_A[1]
ADDR2_A[9]
TDDR_D[1]
ADDR2_A[0-12]
ADDR2_BA[0]
SDDR_D[7]
ADDR2_D[13]
BDDR2_D[9]
SDDR_A[9]
TDDR_A[11]
SDDR_BA[0]
BDDR2_D[12]
SDDR_A[1]
ADDR2_A[3]
ADDR2_D[15]
BDDR2_D[12]
SDDR_A[0]
TDDR_D[0-15]
SDDR_D[4]
/TDDR_RAS
ADDR2_A[3]
BDDR2_D[1]
BDDR2_A[2]
BDDR2_D[1]
ADDR2_D[2]
BDDR2_A[3]
TDDR_DQM1_P
TDDR_A[9]
SDDR_D[15]
TDDR_A[5]
ADDR2_D[6]
TDDR_D[15]
ADDR2_D[7]
BDDR2_D[14]
/SDDR_WE
SDDR_DQS1_P
SDDR_DQM1_P
SDDR_DQS1_N
SDDR_CKE
/SDDR_CK
SDDR_CK
ADDR2_BA[2]
SDDR_BA[2]
SDDR_ODT
R12
56
R33
56
R27
56
AR13
56
C20
0.1uF
AR10
56
C24
0.1uF
R41
56
R8
33
C22
0.1uF
C4
0.1uF
R14
56
+1.8V_S_DDR
+1.8V_S_DDR
C6
0.1uF
C10
0.1uF
R37
56
C35
0.1uF
AR12
56
C31
0.1uF
R7
56
AR9
56
C23
10uF
C12
0.1uF
C37
0.1uF
C27
0.1uF
R39
56
C32
0.1uF
R10
56
R36
56
AR3
56
R20
56
AR1
56
C29
0.1uF
C13
10uF
R30
56
AR7
56
R22
56
AR2
56
R45
150
OPT
AR14
56
C9
0.1uF
R19
56
C34
0.1uF
C2
1000pF
C3
10uF
R17
56
C18
1000pF
R6
56
R43
56
C8
0.1uF
C38
0.1uF
AR4
56
R9
33
+1.8V_S_DDR
C5
0.1uF
R2
150
OPT
R42
56
AR8
56
R40
56
R16
56
C30
10uF
IC2
HYB18TC512160B2F-2.5 
QIMONDA
J2
VREF
J8
CK
H2
VSSQ2
B7
UDQS
N8
A4
P8
A8
L1
NC4
L2
BA0
R8
NC3
K7
RAS
F8
VSSQ3
F3
LDM
P3
A9
M3
A1
N3
A5
K8
CK
R3
NC5
L3
BA1
J7
VSSDL
L7
CAS
F2
VSSQ4
B3
UDM
M2
A10/AP
K2
CKE
R7
NC6
M7
A2
N7
A6
M8
A0
J1
VDDL
K3
WE
E8
LDQS
P7
A11
K9
ODT
A2
NC1
N2
A3
P2
A7
H8
VSSQ1
F7
LDQS
A8
UDQS
R2
A12
L8
CS
E2
NC2
E7
VSSQ5
D8
VSSQ6
D2
VSSQ7
A7
VSSQ8
B8
VSSQ9
B2
VSSQ10
P9
VSS1
N1
VSS2
J3
VSS3
E3
VSS4
A3
VSS5
G9
VDDQ1
G7
VDDQ2
G3
VDDQ3
G1
VDDQ4
E9
VDDQ5
C9
VDDQ6
C7
VDDQ7
C3
VDDQ8
C1
VDDQ9
A9
VDDQ10
R1
VDD1
M9
VDD2
J9
VDD3
E1
VDD4
A1
VDD5
B9
DQ15
B1
DQ14
D9
DQ13
D1
DQ12
D3
DQ11
D7
DQ10
C2
DQ9
C8
DQ8
F9
DQ7
F1
DQ6
H9
DQ5
H1
DQ4
H3
DQ3
H7
DQ2
G2
DQ1
G8
DQ0
+1.8V_S_DDR
+1.8V_S_DDR
C1
0.1uF
AR6
56
R23
1K
1%
R11
56
R21 56
+1.8V_S_DDR
C25
0.1uF
R31
33
R44
1K
1%
R35
56
C39
0.1uF
C41
0.1uF
AR5
56
C11
0.1uF
R18
56
+1.8V_DDR
+1.8V_S_DDR
R32
33
R5
1K
1%
C42
1000pF
AR11
56
C7
0.1uF
R38
56
R15
56
C36
0.1uF
+1.8V_S_DDR
R4
1K
1%
C15
0.1uF
R24
1K
1%
C19
0.1uF
L1
BLM18PG121SN1D
R34
56
C40
0.1uF
C14
0.1uF
R13
56
R28
56
R47
1K
1%
C33
0.1uF
C21
0.1uF
C16
0.1uF
C43
0.1uF
C17
0.1uF
R29
56
IC1
HYB18TC1G160C2F-2.5
QIMONDA
J2
VREF
J8
CK
H2
VSSQ2
B7
UDQS
N8
A4
P8
A8
L1
BA2
L2
BA0
R8
NC3
K7
RAS
F8
VSSQ3
F3
LDM
P3
A9
M3
A1
N3
A5
K8
CK
R3
NC4
L3
BA1
J7
VSSDL
L7
CAS
F2
VSSQ4
B3
UDM
M2
A10/AP
K2
CKE
R7
NC5
M7
A2
N7
A6
M8
A0
J1
VDDL
K3
WE
E8
LDQS
P7
A11
K9
ODT
A2
NC1
N2
A3
P2
A7
H8
VSSQ1
F7
LDQS
A8
UDQS
R2
A12
L8
CS
E2
NC2
E7
VSSQ5
D8
VSSQ6
D2
VSSQ7
A7
VSSQ8
B8
VSSQ9
B2
VSSQ10
P9
VSS1
N1
VSS2
J3
VSS3
E3
VSS4
A3
VSS5
G9
VDDQ1
G7
VDDQ2
G3
VDDQ3
G1
VDDQ4
E9
VDDQ5
C9
VDDQ6
C7
VDDQ7
C3
VDDQ8
C1
VDDQ9
A9
VDDQ10
R1
VDD1
M9
VDD2
J9
VDD3
E1
VDD4
A1
VDD5
B9
DQ15
B1
DQ14
D9
DQ13
D1
DQ12
D3
DQ11
D7
DQ10
C2
DQ9
C8
DQ8
F9
DQ7
F1
DQ6
H9
DQ5
H1
DQ4
H3
DQ3
H7
DQ2
G2
DQ1
G8
DQ0
R1
56
R48
0
OPT
R49
0
OPT
R50
0
OPT
+1.8V_S_DDR
IC600
LGE3369A (Saturn6 Non RM)
B_DDR2_A0
T26
B_DDR2_A1
AF26
B_DDR2_A2
T25
B_DDR2_A3
AF23
B_DDR2_A4
T24
B_DDR2_A5
AE23
B_DDR2_A6
R26
B_DDR2_A7
AD22
B_DDR2_A8
R25
B_DDR2_A9
AC22
B_DDR2_A10
AD23
B_DDR2_A11
R24
B_DDR2_A12
AE22
B_DDR2_BA0
AC23
B_DDR2_BA1
AC24
B_DDR2_BA2
AB22
B_DDR2_MCLK
V25
/B_DDR2_MCLK
V24
B_DDR2_CKE
AB23
B_DDR2_ODT
U26
/B_DDR2_RAS
U25
/B_DDR2_CAS
U24
/B_DDR2_WE
AB24
B_DDR2_DQS0
AB26
B_DDR2_DQS1
AA26
B_DDR2_DQM0
AC25
B_DDR2_DQM1
AC26
B_DDR2_DQSB0
AB25
B_DDR2_DQSB1
AA25
B_DDR2_DQ0
W25
B_DDR2_DQ1
AE26
B_DDR2_DQ2
W24
B_DDR2_DQ3
AF24
B_DDR2_DQ4
AF25
B_DDR2_DQ5
V26
B_DDR2_DQ6
AE25
B_DDR2_DQ7
W26
B_DDR2_DQ8
Y26
B_DDR2_DQ9
AD25
B_DDR2_DQ10
Y25
B_DDR2_DQ11
AE24
B_DDR2_DQ12
AD26
B_DDR2_DQ13
Y24
B_DDR2_DQ14
AD24
B_DDR2_DQ15
AA24
A_MVREF
D15
A_DDR2_A0
C13
A_DDR2_A1
A22
A_DDR2_A2
B13
A_DDR2_A3
C22
A_DDR2_A4
A13
A_DDR2_A5
A23
A_DDR2_A6
C12
A_DDR2_A7
B23
A_DDR2_A8
B12
A_DDR2_A9
C23
A_DDR2_A10
B22
A_DDR2_A11
A12
A_DDR2_A12
A24
A_DDR2_BA0
C24
A_DDR2_BA1
B24
A_DDR2_BA2
D24
A_DDR2_MCLK
B14
/A_DDR2_MCLK
A14
A_DDR2_CKE
D23
A_DDR2_ODT
D14
/A_DDR2_RAS
D13
/A_DDR2_CAS
D12
/A_DDR2_WE
D22
A_DDR2_DQS0
B18
A_DDR2_DQS1
C17
A_DDR2_DQM0
C18
A_DDR2_DQM1
A19
A_DDR2_DQSB0
A18
A_DDR2_DQSB1
B17
A_DDR2_DQ0
B15
A_DDR2_DQ1
A21
A_DDR2_DQ2
A15
A_DDR2_DQ3
B21
A_DDR2_DQ4
C21
A_DDR2_DQ5
C14
A_DDR2_DQ6
C20
A_DDR2_DQ7
C15
A_DDR2_DQ8
C16
A_DDR2_DQ9
C19
A_DDR2_DQ10
B16
A_DDR2_DQ11
B20
A_DDR2_DQ12
A20
A_DDR2_DQ13
A16
A_DDR2_DQ14
B19
A_DDR2_DQ15
A17
IC2-*1
H5PS5162FFR-S6C
HYNIX
J2
VREF
J8
CK
H2
VSSQ2
B7
UDQS
N8
A4
P8
A8
L1
NC4
L2
BA0
R8
NC3
K7
RAS
F8
VSSQ3
F3
LDM
P3
A9
M3
A1
N3
A5
K8
CK
R3
NC5
L3
BA1
J7
VSSDL
L7
CAS
F2
VSSQ4
B3
UDM
M2
A10/AP
K2
CKE
R7
NC6
M7
A2
N7
A6
M8
A0
J1
VDDL
K3
WE
E8
LDQS
P7
A11
K9
ODT
A2
NC1
N2
A3
P2
A7
H8
VSSQ1
F7
LDQS
A8
UDQS
R2
A12
L8
CS
E2
NC2
E7
VSSQ5
D8
VSSQ6
D2
VSSQ7
A7
VSSQ8
B8
VSSQ9
B2
VSSQ10
P9
VSS1
N1
VSS2
J3
VSS3
E3
VSS4
A3
VSS5
G9
VDDQ1
G7
VDDQ2
G3
VDDQ3
G1
VDDQ4
E9
VDDQ5
C9
VDDQ6
C7
VDDQ7
C3
VDDQ8
C1
VDDQ9
A9
VDDQ10
R1
VDD1
M9
VDD2
J9
VDD3
E1
VDD4
A1
VDD5
B9
DQ15
B1
DQ14
D9
DQ13
D1
DQ12
D3
DQ11
D7
DQ10
C2
DQ9
C8
DQ8
F9
DQ7
F1
DQ6
H9
DQ5
H1
DQ4
H3
DQ3
H7
DQ2
G2
DQ1
G8
DQ0
IC1-*1
HY5PS1G1631CFP-S6
HYNIX
J2
VREF
J8
CK
H2
VSSQ2
B7
UDQS
N8
A4
P8
A8
L1
BA2
L2
BA0
R8
NC3
K7
RAS
F8
VSSQ3
F3
LDM
P3
A9
M3
A1
N3
A5
K8
CK
R3
NC5
L3
BA1
J7
VSSDL
L7
CAS
F2
VSSQ4
B3
UDM
M2
A10/AP
K2
CKE
R7
NC6
M7
A2
N7
A6
M8
A0
J1
VDDL
K3
WE
E8
LDQS
P7
A11
K9
ODT
A2
NC1
N2
A3
P2
A7
H8
VSSQ1
F7
LDQS
A8
UDQS
R2
A12
L8
CS
E2
NC2
E7
VSSQ5
D8
VSSQ6
D2
VSSQ7
A7
VSSQ8
B8
VSSQ9
B2
VSSQ10
P9
VSS1
N1
VSS2
J3
VSS3
E3
VSS4
A3
VSS5
G9
VDDQ1
G7
VDDQ2
G3
VDDQ3
G1
VDDQ4
E9
VDDQ5
C9
VDDQ6
C7
VDDQ7
C3
VDDQ8
C1
VDDQ9
A9
VDDQ10
R1
VDD1
M9
VDD2
J9
VDD3
E1
VDD4
A1
VDD5
B9
DQ15
B1
DQ14
D9
DQ13
D1
DQ12
D3
DQ11
D7
DQ10
C2
DQ9
C8
DQ8
F9
DQ7
F1
DQ6
H9
DQ5
H1
DQ4
H3
DQ3
H7
DQ2
G2
DQ1
G8
DQ0
DDR2 1.8V By CAP - Place these Caps near Memory
[E1]
[D1]
[L9]
[N5]
[N4]
[N12]
[N13]
THE    SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE    SYMBOL MARK OF THE SCHEMETIC.
SL90
09/06/24
LVDS/FRC
8     10
URSA_DQ[2]
URSA_B+[4]
URSA_DCK-
URSA_C+[4]
URSA_D+[2]
URSA_DQ[17]
URSA_C-[2]
URSA_A+[0]
URSA_DQ[24]
URSA_A+[3]
URSA_A-[4]
URSA_A+[0]
URSA_C-[4]
URSA_B+[0]
URSA_C-[3]
URSA_C+[0]
URSA_A-[1]
URSA_DQ[26]
URSA_A[5]
URSA_DQ[0]
URSA_DQ[0-31]
URSA_A-[2]
URSA_A[1]
URSA_D+[1]
URSA_B+[0]
URSA_D+[0]
URSA_A[10]
URSA_A+[2]
URSA_DQ[9]
URSA_C-[4]
URSA_D-[2]
URSA_A-[3]
URSA_C-[0]
URSA_C+[0]
URSA_B-[1]
URSA_DQ[5]
URSA_DQ[18]
URSA_B+[3]
URSA_DQ[8]
URSA_B-[0]
URSA_B-[1]
URSA_A-[3]
URSA_A+[3]
URSA_DQ[6]
URSA_B-[2]
URSA_A[12]
URSA_A[2]
URSA_CCK+
URSA_CCK+
URSA_DQ[21]
URSA_B-[4]
URSA_DQ[25]
URSA_B+[1]
URSA_C+[2]
URSA_DQ[27]
URSA_DCK+
URSA_DQ[1]
URSA_D+[4]
URSA_A+[1]
URSA_ACK+
URSA_DQ[13]
URSA_DQ[30]
URSA_A[11]
URSA_B+[2]
URSA_DQ[15]
URSA_A-[0]
URSA_BCK-
URSA_A[6]
URSA_B+[1]
URSA_DQ[31]
URSA_BCK+
URSA_DQ[10]
URSA_B-[2]
URSA_DQ[14]
URSA_B+[3]
URSA_DQ[23]
URSA_DQ[28]
URSA_C-[3]
URSA_B-[3]
URSA_D-[3]
URSA_C+[3]
URSA_C+[1]
URSA_D-[1]
URSA_A[9]
URSA_D+[4]
URSA_D-[3]
URSA_C-[1]
URSA_D+[3]
URSA_BCK-
URSA_A-[4]
URSA_C+[2]
URSA_B+[2]
URSA_DQ[12]
URSA_C-[1]
URSA_C-[0]
URSA_B-[3]
URSA_C+[1]
URSA_A+[4]
URSA_D-[0]
URSA_D+[1]
URSA_CCK-
URSA_D-[4]
URSA_A[0]
URSA_A+[1]
URSA_DQ[11]
URSA_A-[1]
URSA_D-[0]
URSA_A[8]
URSA_DQ[7]
URSA_DCK+
URSA_A[7]
URSA_B+[4]
URSA_C-[2]
URSA_D+[2]
URSA_D-[4]
URSA_ACK-
URSA_DQ[3]
URSA_DQ[29]
URSA_D-[2]
URSA_DQ[19]
URSA_D+[0]
URSA_BCK+
URSA_A-[0]
URSA_A+[4]
URSA_D+[3]
URSA_DQ[16]
URSA_DCK-
URSA_A+[2]
URSA_DQ[4]
URSA_C+[3]
URSA_DQ[22]
URSA_A-[2]
URSA_CCK-
URSA_A[3]
URSA_A[4]
URSA_D-[1]
URSA_B-[0]
URSA_ACK+
URSA_ACK-
URSA_DQ[20]
URSA_C+[4]
URSA_B-[4]
URSA_RASZ
MEMC_RXO0-
006:R36
+3.3V_MEMC
+3.3V_MEMC
R812
100
URSA_DQS3
009:Q13
R843
0
MEMC_RXE4+
006:R37
C
8
2
9
0
.
1
u
F
URSA_CASZ
MEMC_RXE2-
006:R38
M_SPI_CK
URSA_DQSB3
009:Q12
MEMC_RXO0+
006:R36
URSA_WEZ
MEMC_RXE3-
006:R37
C849
1000pF
URSA_MCLK
009:Q16
C828
0.1uF
C822
0.1uF
C820
0.1uF
OPC_EN
MEMC_RXO2-
006:R35
MEMC_RESET
006:AB20
R842
0
OPC(V4)
R809
1K
OPT
R853
2.2K
C
8
3
4
0.1uF
L806
BLM18PG121SN1D
R821
100
C
8
3
2
0.1uF
+3.3V_MEMC
L800
BLM18PG121SN1D
C805
1uF
URSA_BA1
R852
2.2K
M_SPI_DI
R845
0
OPT
+3.3V_ST
R854
0
OPT
R846
0
OPT
MEMC_RXO1-
006:R35
URSA_BA0
M_SPI_DO
C850
0.1uF
OPT
C815
10uF
10V
C816
10uF
R808
1K
R823
100
URSA_MCLKE
M_SPI_CZ
C811
22uF
16V
R827
1K
OPT
MEMC_SCL
006:AI5
C858
10uF
10V
R837
100
C841
0.1uF
C807
10uF
10V
MEMC_RXO2+
006:R35
R851
1K
C
8
3
6
0
.
1
u
F
R850
1K
OPT
+5V_GENERAL
URSA_A[0-12]
L805
BLM18PG121SN1D
MEMC_RXO4+
006:R34
R835
0
MEMC_RXO3-
006:R34
C
8
3
1
0.1uF
R828
1K
PWM_DIM
M_XTALI
008:W26
C825
0.1uF
C823
1uF
MEMC_RXE0-
006:R38
C824
0.1uF
M_SPI_CZ
008:AG9
C
8
3
7
0
.
1
u
F
MEMC_RXO3+
006:R35
R811
10K
M_SPI_DO
008:AG9
BIT_SEL
MEMC_RXOC-
006:R33
C848
22uF
25V
OPT
ISP_TXD_TR
008:J22
C847
0.1uF
URSA_MCLKZ
009:Q15
URSA_DQSB0
C
8
1
4
0
.
1
u
F
R814
100
C845
0.1uF
URSA_MCLK1
C856
0.1uF
16V
MEMC_RXOC+
006:R34
MEMC_RXEC+
006:R36
C804
10uF
10V
URSA_ODT
009:Q15;009:Y15
URSA_DQS1
R848
1K
OPT
URSA_MCLKZ1
MEMC_RXE3+
006:R37
URSA_DQ[0-31]
009:D21;009:AL21
URSA_DQSB1
C
8
3
0
0
.
1
u
F
OPC_OUT1
+3.3V_MEMC
URSA_DQM3
009:Q13
L804
BLM18PG121SN1D
C819
0.1uF
C
8
1
7
0
.
1
u
F
C827
0
.
1
u
F
LVDS_SEL
R815
100
R819
100
+1.8V_MEMC
M_SPI_CK
008:AG9
M_SPI_DI
008:AG9
C
8
5
1
0
.
1
u
F
X800
12MHz
R806
56
R824
0
C821
0.1uF
R813
100
R826
1K
R804
1M
R803
10K
R822
100
C809
10uF
R818
100
R802
56
C
8
3
8
0
.
1
u
F
MEMC_RXE0+
006:R39
R801
56
C812
10uF
C
8
0
3
0
.
1
u
F
C846
0.1uF
URSA_DQM1
R820
100
C
8
5
2
0
.
1
u
F
R810
10K
C818
0.1uF
C
8
3
9
0
.
1
u
F
R838
100
R807
56
+3.3V_MEMC
R836
0
C826
0.1uF
C844
0.1uF
C801
15pF
C813
10uF
MEMC_RXEC-
006:R36
+3.3V_MEMC
ISP_RXD_TR
008:J23
R849
1K
URSA_DQM0
LVDS_SEL
ISP_RXD_TR
008:E10
R817
100
+1.26V_MEMC
MEMC_RXE4-
006:R37
URSA_DQS0
R816
100
MEMC_RXE1+
006:R38
+3.3V_MEMC
MEMC_RXO4-
006:R34
C800
15pF
R833
0
OPT
R847
0
OPC(V4)
C810
10uF
M_XTALO
008:W26
R805
0
OPT
C854
0.1uF
C
8
3
3
0.1uF
OPC_OUT2
M_XTALO
008:J28
+3.3V_MEMC
+3.3V_MEMC
L803
BLM18PG121SN1D
URSA_DQM2
009:Q13
C
8
4
2
0
.
1
u
F
R829
1K
OPT
L801
BLM18PG121SN1D
M_XTALI
008:M28
C
8
3
5
0.1uF
L807
CB3216PA501E
URSA_DQS2
009:Q13
MEMC_RXE2+
006:R38
IC800
W25X20AVSNIG
3
WP
2
DO
4
GND
1
CS
5
DIO
6
CLK
7
HOLD
8
VCC
ISP_TXD_TR
008:E9
MEMC_SDA
006:AI5
C857
0.1uF
16V
C840
0.1uF
L802
BLM18PG121SN1D
URSA_DQSB2
009:Q12
C
8
0
2
0
.
1
u
F
C806
10uF
12V_TCON
C855
0.1uF
C853
0.1uF
C808
22uF
16V
R831
10K
MEMC_RXE1-
006:R38
C
8
4
3
0
.
1
u
F
R825
820
MEMC_RXO1+
006:R35
IC801
LGE7329A
E1
SDAS
D1
SCLS
F1
GPIO[8]
G1
GPIO[9]
K8
GND_14
E5
VDDC_1
E2
GPIO[10]
F2
GPIO[11]
F3
GPIO[12]
G2
GPIO[13]
M4
GPIO[22]
M5
GPIO[23]
G3
GPIO[14]
E4
GPIO[15]
F4
GPIO[16]
G4
GPIO[17]
H4
GPIO[18]
J4
GPIO[19]
K4
GPIO[20]
L4
GPIO[21]
J6
VDDP_2
H9
GND_7
F6
VDDC_2
H1
MDATA[20]
H2
MDATA[19]
H3
MDATA[17]
J1
MDATA[22]
J2
MDATA[27]
J3
MDATA[28]
K1
MDATA[25]
K2
MDATA[30]
K6
AVDD_DDR_2
K3
DQM[3]
L1
DQM[2]
J8
GND_10
L2
DQS[2]
L3
DQSB[2]
L6
AVDD_DDR_4
L8
VDDP_3
H10
GND_8
M1
DQS[3]
M2
DQSB[3]
L7
AVDD_DDR_5
M3
MDATA[31]
N1
MDATA[24]
J9
GND_11
N2
MDATA[26]
N3
MDATA[29]
L10
AVDD_DDR_6
P1
MDATA[23]
R1
MDATA[16]
T1
MDATA[18]
T2
MDATA[21]
R2
MCLK[0]
P2
MCLKZ[0]
G7
GND_1
L9
AVDD_MEMPLL
N5
MVREF
N4
ODT
T3
RASZ
R3
CASZ
P3
MADR[0]
T4
MADR[2]
R4
MADR[4]
J10
GND_12
P4
MADR[6]
T5
MADR[8]
R5
MADR[11]
P5
WEZ
T6
BADR[1]
R6
BADR[0]
P6
MADR[1]
T7
MADR[10]
L11
AVDD_DDR_7
R7
MADR[5]
P7
MADR[9]
T8
MADR[12]
R8
MADR[7]
P8
MADR[3]
N8
MCLKE
K10
GND_16
F7
VDDC_3
T9
MDATA[4]
R9
MDATA[3]
K7
GND_13
P9
MDATA[1]
T10
MDATA[6]
K11
AVDD_DDR_3
R10
MDATA[11]
P10
MDATA[12]
T11
MDATA[9]
R11
MDATA[14]
J11
AVDD_DDR_1
P11
DQM[1]
T12
DQM[0]
R12
DQS[0]
P12
DQSB[0]
H11
VDDP_1
T13
DQS[1]
R13
DQSB[1]
P13
MDATA[15]
T14
MDATA[8]
R14
MDATA[10]
P14
MDATA[13]
T15
MDATA[7]
R15
MDATA[0]
P15
MDATA[2]
T16
MDATA[5]
R16
MCLK[1]
P16
MCLKZ[1]
N9
GPIO[26]
N10
GPIO[27]
N11
GND_17
M11
RESET
G6
VDDC_4
N12
GPIO[28]
N13
GPIO[29]
N14
GPIO[30]
L13
SCK
M13
SDI
M12
SDO
K13
CSZ
L12
PWM1
K12
PWM0
J13
GPIO[0]
H13
GPIO[1]
G13
GPIO[2]
F13
GPIO[3]
E13
GPIO[4]
F12
GPIO[5]
D14
GPIO[6]
E12
GPIO[7]
N6
GPIO[24]
H6
VDDC_5
N15
LVD4M
N16
LVD4P
M14
LVD3M
M15
LVD3P
F8
AVDD_33_1
M16
LVDCKM
L16
LVDCKP
L15
LVD2M
L14
LVD2P
G9
GND_3
K14
LVD1M
J14
LVD1P
J16
LVD0M
J15
LVD0P
H15
LVC4M
H16
LVC4P
H14
LVC3M
G14
LVC3P
G16
LVCCKM
G15
LVCCKP
F15
LVC2M
F16
LVC2P
F14
LVC1M
E14
LVC1P
E16
LVC0M
E15
LVC0P
G10
GND_4
F9
AVDD_33_2
D16
LVB4M
D15
LVB4P
C16
LVB3M
B16
LVB3P
A16
LVBCKM
A15
LVBCKP
B15
LVB2M
C15
LVB2P
D2
GPIO_3
E3
GPIO_10
E10
GPIO_11
D10
GPIO_7
D8
GPIO_5
D12
REXT
C14
LVB1M
C13
LVB1P
A13
LVB0M
B13
LVB0P
D7
GPIO_4
D9
GPIO_6
B12
LVA4M
A12
LVA4P
C12
LVA3M
C11
LVA3P
A11
LVACKM
B11
LVACKP
B10
LVA2M
A10
LVA2P
C10
LVA1M
C9
LVA1P
A9
LVA0M
B9
LVA0P
F10
AVDD_PLL
G8
GND_2
D11
GPIO_8
D13
GPIO_9
E11
GPIO_12
N7
GPIO[25]
D6
SCLM
D5
SDAM
A14
GPIO_1
B14
GPIO_2
D3
XIN
D4
XOUT
K16
GPIO_14
K15
GPIO_13
H7
GND_5
G11
AVDD_LVDS_2
B8
RO0N
A8
RO0P
C8
RO1N
C7
RO1P
A7
RO2N
B7
RO2P
B6
ROCKN
A6
ROCKP
C6
RO3N
C5
RO3P
A5
RO4N
B5
RO4P
H8
GND_6
F11
AVDD_LVDS_1
B4
RE0N
A4
RE0P
C4
RE1N
C3
RE1P
A3
RE2N
B3
RE2P
B2
RECKN
A2
RECKP
C2
RE3N
C1
RE3P
A1
RE4N
B1
RE4P
GND_9
J7
GND_15 K9
P800
TF05-51S
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
P801
TF05-41S
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
R855
0
R856
0
OPT
+3.3V_MEMC
R857
4.7K
OPT
P803
WAFER-STRAIGHT
1
SPK_R-
2
SPK_R+
3
SPK_L-
4
SPK_L+
5
M
D
S
6
2
1
1
0
2
0
1
G
A
S
3
M
D
S
6
2
1
1
0
2
0
1
G
A
S
1
M
D
S
6
2
1
1
0
2
0
1
G
A
S
4
M
D
S
6
2
1
1
0
2
0
1
G
A
S
5
M
D
S
6
2
1
1
0
2
0
1
G
A
S
6
M
D
S
6
2
1
1
0
2
0
1
G
A
S
2
M
D
S
6
2
1
1
0
2
0
1
G
A
S
7
M
D
S
6
2
1
1
0
2
0
1
G
A
S
1
1
M
D
S
6
2
1
1
0
2
0
1
G
A
S
1
0
M
D
S
6
2
1
1
0
2
0
1
G
A
S
8
M
D
S
6
2
1
1
0
2
0
1
G
A
S
9
                    GPIO12  GPIO14
Non M+S LVDS         LOW     LOW
M+S 42" Mini LVDS    LOW     HIGH
M+S 47" Mini LVDS    HIGH    LOW
M+S 37" Mini LVDS    HIGH    HIGH
SPI FLASH
PI Result
PWM1
EEPROM
PWM0
HIGH
SPI
PI Result
HIGH
I2C
HIGH
ISP Port for MEMC
HIGH
LOW
HIGH
LOW
HIGH
HIGH
XTAL
GPIO8
SMD Gasket Option for FRC one-board
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