LG 37LH50YR (CHASSIS:LP91B) Service Manual ▷ View online
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
MEMC_BA0
0.1uF
C1211
+1.8V_MEMC
22uF
C1247
MEMC_MCLKE
0.1uF
C1213
56
AR1204
0.1uF
C1215
MEMC_DQM0
56
R1216
1K
1%
R1223
0
R1233
0.1uF
C1246
MEMC_BA1
56
R1205
10uF
25
V
C1253
0.1uF
C1240
MEMC_DQSB3
0.1uF
C1236
22
AR1205
1000pF
C1239
+1.8V_MEMC_DDR
MEMC_DQ[16-31]
0.1uF
C1230
100uF
16V
C1251
MEMC_BA1
MEMC_BA0
A_URSA_WEZ
MEMC_MCLKZ
22
AR1206
0.1uF
C1209
56
AR1202
0.1uF
C1225
MEMC_DQ[0-15]
56
R1219
BD9130EFJ-E2
IC1203
3
ITH
2
VCC
4
GND
1
ADJ
5
PGND
6
SW
7
PVCC
8
EN
+1.8V_MEMC_DDR
MEMC_MCLKZ1
+1.8V_MEMC_DDR
0.1uF
C1250
0.1uF
C1207
150 READY
R1201
BLM18PG121SN1D L1201
B_URSA_WEZ
MEMC_DQS1
+1.8V_MEMC
22
AR1207
MEMC_MCLKE
0.1uF
C1261
B_URSA_MCLKE
B_URSA_WEZ
56
R1210
10K
R1227
10K
1%
R1231
22
R1213
A_URSA_BA1
MEMC_A[0-12]
A_URSA_CASZ
0.1uF
C1232
A_URSA_BA1
P_12V
22
R1202
22
AR1210
17.4K
1%
R1232
B_URSA_BA1
39K
R1236
18nF
16
V
C1259
MEMC_DQSB1
0.1uF
C1252
30K
1%
R1229
+1.8V_MEMC
DDRA_A[0-12]
MEMC_CASZ
0.1uF
C1218
0.1uF
C1241
0.1uF
C1229
0.1uF
C1206
MEMC_CASZ
56
R1209
330pF
C1245
B_URSA_BA0
0.1uF
C1238
0.1uF
C1210
BLM18PG121SN1D L1202
22
AR1211
10uF
25
V
C1254
56
AR1214
56
AR1203
A_URSA_BA0
MEMC_RASZ
22
AR1209
0.1uF
C1262
100uF
C1243
12K
R1237
0.1uF
16V
C1221
A_URSA_CASZ
0.1uF
C1231
0.1uF
C1214
10uF
16
V
C1257
MEMC_DQS2
0.1uF
C1234
56
R1215
150
READY
R1220
MEMC_ODT
A_URSA_RASZ
DDR_DQ[0-15]
22
R1212
MEMC_MCLK1
0.1uF
C1220
0.1uF
C1267
A_URSA_BA0
0.1uF
C1235
22
AR1217
56
R1208
MEMC_DQM1
0.1uF
C1217
0.1uF
C1226
10uF
10V
C1202
22
R1211
10uF
C1227
+1.8V_MEMC
+1.8V_MEMC_DDR
B_URSA_CASZ
22
AR1218
MEMC_DQSB2
0.1uF
C1208
A_URSA_MCLKE
10uF
16
V
C1258
MEMC_RASZ
56
AR1216
B_URSA_RASZ
MEMC_WEZ
10uF
C1222
B_URSA_CASZ
0.1uF
C1223
MEMC_DQM3
MP2212DN
IC1205
3I
N
2
GND
4B
S
1F
B
5
VCC
6
SW_1
7
SW_2
8
EN/SYNC
0.1uF
C1228
0.1uF
C1216
MEMC_DQM2
A_URSA_MCLKE
56
AR1201
0.1uF
C1219
22
AR1208
18K
R1225
10
R1234
0.1uF
C1201
B_URSA_BA1
1uF
C1264
10uF
16
V
C1260
DDR_DQ[0-15]
A_URSA_RASZ
0.1uF
C1224
+3.3V_MEMC
39K
1%
R1228
22uF
C1244
10uF
C1212
1K
R1230
A_URSA_WEZ
1K
1%
R1222
+1.8V_MEMC_DDR
22
AR1212
+1.8V_MEMC_DDR
22
R1204
10K
R1235
+1.8V_MEMC_DDR
0.1uF
C1204
B_URSA_MCLKE
MEMC_DQS3
DDR_DQ[16-31]
56
R1207
+1.8V_MEMC_DDR
DDRB_A[0-12]
10uF
C1203
0.1uF
C1237
DDRB_A[0-12]
22
R1203
+1.26V_MEMC
10uF
10
V
C1249
1000pF
C1242
DDR_DQ[16-31]
56
R1217
56
AR1215
56
R1218
B_URSA_RASZ
0.1uF
C1233
0.1uF
C1248
56
AR1213
MEMC_DQSB0
56
R1206
1K
1%
R1221
56
R1214
MEMC_DQS0
MEMC_ODT
1K
1%
R1224
MEMC_MCLK
MEMC_WEZ
1uF
25
V
C1255
B_URSA_BA0
+3.3V_MEMC
0.1uF
C1205
DDRA_A[0-12]
3.6uH
L1204
APE8953MP
IC1204
3
VOUT_1
2
FB
FB
4
VOUT_2
1
GND
5
VIN
6
VCNTL
7
POK
8E
N
500
L1206
500
L1205
2.2uH
L1203
+5V_MULTI
+5V_MULTI
HYB18TC512160CF-2.5
IC1202
QIMONDA
J2
VREF
J8
CK
H2
VSSQ2
B7
UDQS
N8
A4
P8
A8
L1
NC4
L2
BA0
R8
NC3
K7
RAS
F8
VSSQ3
F3
LDM
P3
A9
M3
A1
N3
A5
K8
CK
R3
NC5
L3
BA1
J7
VSSDL
L7
CAS
F2
VSSQ4
B3
UDM
M2
A10/AP
K2
CKE
R7
NC6
M7
A2
N7
A6
M8
A0
J1
VDDL
K3
WE
E8
LDQS
P7
A11
K9
ODT
A2
NC1
N2
A3
P2
A7
H8
VSSQ1
F7
LDQS
A8
UDQS
R2
A12
L8
CS
E2
NC2
E7
VSSQ5
D8
VSSQ6
D2
VSSQ7
A7
VSSQ8
B
8
VSSQ9
B
2
VSSQ10
P9
VSS1
N
1
VSS2
J3
VSS3
E3
VSS4
A
3
VSS5
G
9
VDDQ1
G
7
VDDQ2
G
3
VDDQ3
G
1
VDDQ4
E9
VDDQ5
C
9
VDDQ6
C
7
VDDQ7
C
3
VDDQ8
C
1
VDDQ9
A
9
VDDQ10
R
1
VDD1
M
9
VDD2
J9
VDD3
E1
VDD4
A
1
VDD5
B
9
DQ15
B
1
DQ14
D9
DQ13
D1
DQ12
D3
DQ11
D7
DQ10
C
2
DQ9
C
8
DQ8
F9
DQ7
F1
DQ6
H
9
DQ5
H
1
DQ4
H
3
DQ3
H
7
DQ2
G
2
DQ1
G
8
DQ0
HYB18TC512160CF-2.5
IC1201
QIMONDA
J2
VREF
J8
CK
H2
VSSQ2
B
7
UDQS
N8
A4
P8
A
8
L1
NC4
L2
BA0
R
8
NC3
K7
RAS
F8
VSSQ3
F3
LDM
P3
A
9
M3
A
1
N3
A5
K8
CK
R
3
NC5
L3
BA1
J7
VSSDL
L7
CAS
F2
VSSQ4
B
3
UDM
M
2
A10/AP
K
2
CKE
R
7
NC6
M7
A
2
N7
A6
M8
A
0
J1
VDDL
K3
WE
E8
LDQS
P7
A11
K
9
ODT
A
2
NC1
N2
A3
P2
A
7
H8
VSSQ1
F7
LDQS
A8
UDQS
R
2
A12
L8
CS
E2
NC2
E7
VSSQ5
D8
VSSQ6
D2
VSSQ7
A7
VSSQ8
B8
VSSQ9
B2
VSSQ10
P9
VSS1
N1
VSS2
J3
VSS3
E3
VSS4
A3
VSS5
G9
VDDQ1
G7
VDDQ2
G3
VDDQ3
G1
VDDQ4
E9
VDDQ5
C9
VDDQ6
C7
VDDQ7
C3
VDDQ8
C1
VDDQ9
A9
VDDQ10
R1
VDD1
M9
VDD2
J9
VDD3
E1
VDD4
A1
VDD5
B9
DQ15
B1
DQ14
D9
DQ13
D1
DQ12
D3
DQ11
D7
DQ10
C2
DQ9
C8
DQ8
F9
DQ7
F1
DQ6
H9
DQ5
H1
DQ4
H3
DQ3
H7
DQ2
G2
DQ1
G8
DQ0
0
R1226
0.47uF
C1256
H5PS5162FFR-S6C
Hynix
IC1201-*1
J2
VREF
J8
CK
H2
VSSQ2
B7
UDQS
N8
A4
P8
A8
L1
NC4
L2
BA0
R8
NC3
K7
RAS
F8
VSSQ3
F3
LDM
P3
A9
M3
A1
N3
A5
K8
CK
R3
NC5
L3
BA1
J7
VSSDL
L7
CAS
F2
VSSQ4
B3
UDM
M2
A10/AP
K2
CKE
R7
NC6
M7
A2
N7
A6
M8
A0
J1
VDDL
K3
WE
E8
LDQS
P7
A11
K9
ODT
A2
NC1
N2
A3
P2
A7
H8
VSSQ1
F7
LDQS
A8
UDQS
R2
A12
L8
CS
E2
NC2
E7
VSSQ5
D8
VSSQ6
D2
VSSQ7
A7
VSSQ8
B8
VSSQ9
B2
VSSQ10
P9
VSS1
N1
VSS2
J3
VSS3
E3
VSS4
A3
VSS5
G9
VDDQ1
G7
VDDQ2
G3
VDDQ3
G1
VDDQ4
E9
VDDQ5
C9
VDDQ6
C7
VDDQ7
C3
VDDQ8
C1
VDDQ9
A9
VDDQ10
R1
VDD1
M9
VDD2
J9
VDD3
E1
VDD4
A1
VDD5
B9
DQ15
B1
DQ14
D9
DQ13
D1
DQ12
D3
DQ11
D7
DQ10
C2
DQ9
C8
DQ8
F9
DQ7
F1
DQ6
H9
DQ5
H1
DQ4
H3
DQ3
H7
DQ2
G2
DQ1
G8
DQ0
H5PS5162FFR-S6C
Hynix
IC1202-*1
J2
VREF
J8
CK
H2
VSSQ2
B7
UDQS
N8
A4
P8
A8
L1
NC4
L2
BA0
R8
NC3
K7
RAS
F8
VSSQ3
F3
LDM
P3
A9
M3
A1
N3
A5
K8
CK
R3
NC5
L3
BA1
J7
VSSDL
L7
CAS
F2
VSSQ4
B3
UDM
M2
A10/AP
K2
CKE
R7
NC6
M7
A2
N7
A6
M8
A0
J1
VDDL
K3
WE
E8
LDQS
P7
A11
K9
ODT
A2
NC1
N2
A3
P2
A7
H8
VSSQ1
F7
LDQS
A8
UDQS
R2
A12
L8
CS
E2
NC2
E7
VSSQ5
D8
VSSQ6
D2
VSSQ7
A7
VSSQ8
B8
VSSQ9
B2
VSSQ10
P9
VSS1
N1
VSS2
J3
VSS3
E3
VSS4
A3
VSS5
G9
VDDQ1
G7
VDDQ2
G3
VDDQ3
G1
VDDQ4
E9
VDDQ5
C9
VDDQ6
C7
VDDQ7
C3
VDDQ8
C1
VDDQ9
A9
VDDQ10
R1
VDD1
M9
VDD2
J9
VDD3
E1
VDD4
A1
VDD5
B9
DQ15
B1
DQ14
D9
DQ13
D1
DQ12
D3
DQ11
D7
DQ10
C2
DQ9
C8
DQ8
F9
DQ7
F1
DQ6
H9
DQ5
H1
DQ4
H3
DQ3
H7
DQ2
G2
DQ1
G8
DQ0
DDR_DQ[24]
MEMC_A[2]
DDR_DQ[28]
DDR_DQ[5]
DDRB_A[7]
DDR_DQ[9]
MEMC_DQ[21]
DDRA_A[4]
DDRB_A[6]
MEMC_A[11]
DDR_DQ[31]
MEMC_A[1]
DDRA_A[6]
DDRB_A[8]
MEMC_DQ[25]
DDR_DQ[13]
MEMC_DQ[12]
DDRA_A[1]
MEMC_A[7]
DDR_DQ[20]
MEMC_DQ[23]
DDRA_A[3]
MEMC_A[11]
MEMC_DQ[30]
MEMC_DQ[24]
MEMC_A[12]
DDRA_A[12]
DDRA_A[11]
DDR_DQ[10]
MEMC_A[4]
MEMC_DQ[6]
DDR_DQ[21]
DDRB_A[0]
MEMC_DQ[22]
MEMC_A[10]
MEMC_DQ[5]
DDRA_A[7]
DDRB_A[9]
DDRA_A[12]
DDR_DQ[26]
MEMC_A[6]
DDRB_A[5]
DDRA_A[9]
DDRA_A[2]
DDR_DQ[26]
DDRB_A[11]
DDR_DQ[9]
MEMC_A[1]
DDR_DQ[8]
DDR_DQ[2]
MEMC_DQ[19]
MEMC_A[3]
MEMC_DQ[18]
MEMC_DQ[16]
DDRA_A[8]
MEMC_DQ[26]
DDR_DQ[23]
MEMC_A[7]
DDR_DQ[21]
DDR_DQ[28]
DDR_DQ[12]
DDR_DQ[30]
DDR_DQ[7]
MEMC_A[8]
MEMC_DQ[0]
DDR_DQ[30]
DDRB_A[4]
MEMC_A[0]
DDRA_A[9]
DDR_DQ[25]
DDR_DQ[20]
DDR_DQ[17]
MEMC_DQ[14]
DDR_DQ[14]
MEMC_A[12]
DDRB_A[5]
DDR_DQ[25]
DDR_DQ[7]
MEMC_A[4]
DDR_DQ[1]
MEMC_A[9]
DDRA_A[10]
DDR_DQ[27]
DDR_DQ[8]
DDR_DQ[29]
MEMC_DQ[3]
DDRB_A[12]
DDRA_A[1]
DDR_DQ[3]
DDR_DQ[27]
MEMC_DQ[15]
MEMC_A[10]
MEMC_DQ[4]
MEMC_A[2]
DDR_DQ[2]
MEMC_DQ[11]
MEMC_DQ[29]
DDR_DQ[4]
DDR_DQ[17]
DDRB_A[4]
MEMC_A[5]
DDRA_A[4]
DDR_DQ[29]
DDRA_A[0]
DDRB_A[6]
DDR_DQ[22]
DDR_DQ[19]
DDR_DQ[15]
DDR_DQ[11]
MEMC_DQ[8]
DDR_DQ[15]
DDR_DQ[16]
DDR_DQ[5]
DDR_DQ[22]
DDRB_A[1]
DDRA_A[11]
MEMC_A[3]
DDR_DQ[23]
DDRA_A[3]
DDRA_A[6]
DDR_DQ[24]
MEMC_A[5]
DDR_DQ[10]
MEMC_DQ[13]
DDR_DQ[11]
MEMC_A[0]
DDRB_A[11]
DDR_DQ[1]
DDRB_A[12]
DDRB_A[3]
DDR_DQ[0]
MEMC_DQ[1]
MEMC_DQ[9]
MEMC_DQ[27]
MEMC_DQ[17]
DDRB_A[7]
MEMC_DQ[28]
MEMC_DQ[20]
DDR_DQ[14]
DDRA_A[5]
DDRB_A[2]
DDR_DQ[18]
MEMC_A[6]
DDR_DQ[4]
DDRB_A[3]
DDRA_A[2]
DDR_DQ[6]
DDRB_A[2]
DDRB_A[8]
MEMC_DQ[7]
DDRA_A[0]
MEMC_DQ[10]
MEMC_DQ[31]
MEMC_DQ[2]
DDRB_A[10]
DDRB_A[0]
MEMC_A[9]
DDRA_A[7]
DDR_DQ[18]
DDR_DQ[31]
DDR_DQ[16]
DDRB_A[9]
DDRA_A[5]
DDR_DQ[3]
DDRB_A[1]
DDR_DQ[12]
DDR_DQ[19]
DDRA_A[10]
MEMC_A[8]
DDR_DQ[6]
DDRB_A[10]
DDR_DQ[0]
DDR_DQ[13]
DDRA_A[8]
EAX58017401 Mstar LCD LH50
H6 LH50
12 12
MEMC_DDR & POWER
2008/12/23
R2
Vo=0.8(1+R1/R2)
V0 = 0.8(1+R1/R2)
R2
1000 mA @85% efficiency
233 mA+400mA+600mA
2A
V0 = 0.8(1+R1/R2)
DDR2 1.8V By CAP - Place these Caps near Memory
+1.8V_MEMC for DDR
R1
R1
+1.26V Core for MEMC
MAX 3A
600 mA
400mA + 600mA
+3.3V_MEMC
MAX 2A
R1
R2
1300 mA @85% efficiency
DDR2 1.8V By CAP - Place these Caps near Memory
Close to IC1204
Feb., 2009
P/NO : MFL60021522
Feb., 2009
P/NO : MFL60021522
Feb., 2009
P/NO : MFL60021522