Harman Kardon HK 990 (serv.man2) Service Manual ▷ View online
Rev. 1.5 / Feb. 2005
5
Synchronous DRAM Memory 64Mbit (4Mx16bit)
HY57V641620E(L/S)T(P)-xI Series
FUNCTIONAL BLOCK DIAGRAM
1Mbit x 4banks x 16 I/O Synchronous DRAM
Internal Row
Counter
Column
Pre
Decoder
Column Add
Counter
Self refresh
logic & timer
Sense AMP & I/O Gate
I/O Buffer & Logic
Address
Register
Burst
Counter
Mode Register
State Machine
Address Buffers
Bank Select
Column Active
Row Active
CAS Latency
CLK
CKE
CS
RAS
CAS
WE
U/LDQM
A0
A1
A1
BA1
BA0
A11
Row
Pre
Decoder
Refresh
DQ0
DQ15
X-Dec
oder
X-Dec
oder
X-Dec
oder
X-Dec
oder
Y-Decoder
1Mx16 BANK 0
1Mx16 BANK 1
1Mx16 BANK 2
1Mx16 BANK 3
Memory
Cell
Array
Data Out Control
Pipe Line
Control
3
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Publication Number S29AL016D_00 Revision A Amendment 2 Issue Date December 17, 2004
PRELIMINARY
S29AL016D
16 Megabit (2 M x 8-Bit/1 M x 16-Bit)
CMOS 3.0 Volt-only Boot Sector Flash Memory
CMOS 3.0 Volt-only Boot Sector Flash Memory
Data Sheet
Distinctive Characteristics
Architectural Advantages
Single power supply operation
— Full voltage range: 2.7 to 3.6 volt read and write op-
erations for battery-powered applications
Manufactured on 200nm process technology
— Fully compatible with 0.23 µm Am29LV160D and
MBM29LV160E devices
Flexible sector architecture
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and thirty-
one 64 Kbyte sectors (byte mode)
— One 8 Kword, two 4 Kword, one 16 Kword, and thirty-
one 32 Kword sectors (word mode)
Sector Protection features
— A hardware method of locking a sector to prevent any
program or erase operations within that sector
— Sectors can be locked in-system or via programming
equipment
— Temporary Sector Unprotect feature allows code
changes in previously locked sectors
Unlock Bypass Program Command
— Reduces overall programming time when issuing
multiple program command sequences
Top or bottom boot block configurations
available
Compatibility with JEDEC standards
— Pinout and software compatible with single-power
supply Flash
— Superior inadvertent write protection
Performance Characteristics
High performance
— Access times as fast as 70 ns
Ultra low power consumption (typical values
at 5 MHz)
— 200 nA Automatic Sleep mode current
— 200 nA standby mode current
— 9 mA read current
— 20 mA program/erase current
— 200 nA standby mode current
— 9 mA read current
— 20 mA program/erase current
Cycling endurance: 1,000,000 cycles per
sector typical
Data retention: 20 years typical
Package Options
48-ball FBGA
48-pin TSOP
44-pin SOP
48-pin TSOP
44-pin SOP
Software Features
CFI (Common Flash Interface) compliant
— Provides device-specific information to the system,
allowing host software to easily reconfigure for
different Flash devices
different Flash devices
Erase Suspend/Erase Resume
— Suspends an erase operation to read data from, or
program data to, a sector that is not being erased,
then resumes the erase operation
then resumes the erase operation
Data# Polling and toggle bits
— Provides a software method of detecting program or
erase operation completion
Hardware Features
Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting program or
erase cycle completion
3
6
6
S29AL016D
S29AL016D_00_A2 December 17, 2004
P r e l i m i n a r y
Connection Diagrams
A1
A15
A18
A14
A13
A12
A11
A10
A12
A11
A10
A9
A8
A8
A19
NC
WE#
RESET#
NC
NC
NC
RY/BY#
A17
A7
A6
A5
A4
A3
A2
A6
A5
A4
A3
A2
1
16
2
3
4
5
6
7
8
4
5
6
7
8
17
18
18
19
20
21
22
23
24
20
21
22
23
24
9
10
11
12
13
14
15
10
11
12
13
14
15
A16
DQ2
BYTE#
V
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ7
DQ14
DQ6
DQ13
DQ9
DQ1
DQ8
DQ0
DQ1
DQ8
DQ0
OE#
V
V
SS
CE#
A0
A0
DQ5
DQ12
DQ4
DQ12
DQ4
V
CC
DQ11
DQ3
DQ10
DQ3
DQ10
48
33
47
46
45
44
43
42
41
40
39
38
37
36
35
34
45
44
43
42
41
40
39
38
37
36
35
34
25
32
31
30
29
28
27
26
31
30
29
28
27
26
Standard TSOP
1
2
3
4
5
6
7
8
9
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
11
12
13
14
15
16
17
18
19
20
21
22
RESET#
A18
A17
A17
A7
A6
A5
A4
A3
A2
A1
A0
A6
A5
A4
A3
A2
A1
A0
CE#
V
SS
OE#
DQ0
DQ8
DQ1
DQ9
DQ2
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
WE#
A19
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE#
V
A19
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE#
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
Standard SOP
3
7
December 17, 2004 S29AL016D_00_A2
S29AL016D
P r e l i m i n a r y
Connection Diagrams
Special Handling Instructions
Special handling is required for Flash Memory products in FBGA packages.
Flash memory devices in FBGA packages may be damaged if exposed to ultra-
sonic cleaning methods. The package and/or data integrity may be compromised
if the package body is exposed to temperatures above 150°C for prolonged peri-
ods of time.
sonic cleaning methods. The package and/or data integrity may be compromised
if the package body is exposed to temperatures above 150°C for prolonged peri-
ods of time.
A1
B1
C1
D1
E1
F1
G1
H1
A2
B2
C2
D2
E2
F2
G2
H2
A3
B3
C3
D3
E3
F3
G3
H3
A4
B4
C4
D4
E4
F4
G4
H4
A5
B5
C5
D5
E5
F5
G5
H5
A6
B6
C6
D6
E6
F6
G6
H6
DQ15/A-1
V
SS
BYTE#
A16
A15
A14
A12
A13
DQ13
DQ6
DQ14
DQ7
A11
A10
A8
A9
V
CC
DQ4
DQ12
DQ5
A19
NC
RESET#
WE#
DQ11
DQ3
DQ10
DQ2
NC
A18
NC
RY/BY#
DQ9
DQ1
DQ8
DQ0
A5
A6
A17
A7
OE#
V
SS
CE#
A0
A1
A2
A4
A3
FBGA
Top View, Balls Facing Down
38
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