Harman Kardon HD 755 (serv.man9) Service Manual ▷ View online
HD755
®
PCM1732
SPECIFICATIONS
16-Bit Data Performance
All specifications at +25
°
C, +V
DD
= +V
CC
= +5V, f
S
= 44.1kHz, and SYSCLK = 384f
S
, unless otherwise noted. For discussion of HDCD scaling options, see the
Applications Considerations section of this data sheet.
PCM1732U
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DYNAMIC ANALOG PERFORMANCE,
STANDARD CD, ANALOG HDCD SCALING
STANDARD CD, ANALOG HDCD SCALING
(1)
Total Harmonic Distortion + Noise
V
O
= 0dB
0dBFS
–95
dB
V
O
= –60dB
–37
dB
Dynamic Range
EIAJ A-Weighted
99
dB
Output Voltage, Sine Wave
0dBFS
(2)
0.57V
CC
Vp-p
DYNAMIC ANALOG PERFORMANCE,
HDCD CD, ANALOG HDCD SCALING
HDCD CD, ANALOG HDCD SCALING
(3)
Total Harmonic Distortion + Noise
V
O
= 0dB
0dBFS
–94
dB
V
O
= –60dB
–38
dB
Dynamic Range
EIAJ A-Weighted
(4)
104
dB
Output Voltage, Sine Wave
0dBFS, Without Peak Extend
(2)
0.57V
CC
Vp-p
0dBFS, With Peak Extend
(5)
0.285V
CC
Vp-p
+6dBFS
(5, 6)
0.57V
CC
Vp-p
DYNAMIC ANALOG PERFORMANCE,
Standard CD, Digital HDCD SCALING
Standard CD, Digital HDCD SCALING
(1)
Total Harmonic Distortion + Noise
V
O
= 0dB
0dBFS
–92
dB
V
O
= –60dB
–33
dB
Dynamic Range
EIAJ A-Weighted
96
dB
Output Voltage, Sine Wave
0dBFS
0.285V
CC
Vp-p
DYNAMIC ANALOG PERFORMANCE
HDCD CD, Digital HDCD SCALING
HDCD CD, Digital HDCD SCALING
(2)
Total Harmonic Distortion + Noise
V
O
= 0dB
0dBFS
–91
dB
V
O
= –60dB
–34
dB
Dynamic Range
EIAJ A-Weighted
(4)
104
dB
Output Voltage, Sine Wave
0dBFS
0.285V
CC
Vp-p
+6dBFS
(5)
0.57V
CC
Vp-p
NOTES: (1) Without dither. (2) Gain pin is LOW. (3) With the rectangular PDF dither. (4) Including Peak Extend to +6dBFS. (5) Gain pin is HIGH. (6) +6dBFS is
the full Peak Extend, while dynamic range numbers are with Peak Extend.
the full Peak Extend, while dynamic range numbers are with Peak Extend.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
33
HD755
®
PCM1732
PIN
NAME
I/O
DESCRIPTION
1
LRCIN
IN
Left and Right Clock Input. This clock is equal to
the sampling rate, f
the sampling rate, f
S
.
(1)
2
DIN
IN
Serial Audio Data Input
(1)
3
BCKIN
IN
Bit Clock Input for Serial Audio Data
(1)
4
CLKO
OUT
Buffered System Clock Output.
5
XTI
IN
Oscillator Input/External Clock Input
(2)
6
XTO
OUT
Oscillator Output
7
DGND
—
Digital Ground
8
V
DD
—
Digital Power +5V
9
HDCD
OUT
HDCD Encoded Data Detect
10
V
CC
2R
—
Analog Power +5V, Rch
11
AGND2R
—
Analog Ground, Rch
12
EXTR
—
Common Mode Voltage for Analog Output Amp,
Rch
Rch
13
V
OUT
R
OUT
Analog Voltage Output, Rch
14
AGND1
—
Analog Ground
15
V
CC
1
—
Analog Power +5V
16
V
OUT
L
OUT
Analog Voltage Output, Lch
17
EXTL
—
Common Mode Voltage for Analog Output Amp,
Lch
Lch
18
AGND2L
OUT
Analog Ground, Lch
19
V
CC
2L
—
Analog Power +5V, Lch
20
GAIN
OUT
External (analog) Gain Scaling
21
ZERO
OUT
Zero Data Flag
22
RST
IN
Reset. When this pin is LOW, the digital filter
and modulators are held in reset.
and modulators are held in reset.
(3)
23
CS/IW0
IN
Chip Select/Input Format Selection. When this
pin is LOW, the Mode Control interface is en-
abled.
pin is LOW, the Mode Control interface is en-
abled.
(4)
24
MODE
IN
Mode Control Select: H = Software; L =
Hardware
Hardware
(3)
25
MUTE
IN
Mute Control
(3)
26
MD/FSS
IN
Mode Data/Sampling Rate Range Select
(3)
27
MC/DEM
IN
Mode Clock/De-Emphasis Select
(3)
28
ML/I
2
S
IN
Mode Latch/Input Format Select
(3)
NOTES: (1) Schmitt Trigger input. (2) CMOS logic level input. (3) Schmitt
Trigger input with pull-up resister. (4) Schmitt Trigger input with pull-down
resistor.
Trigger input with pull-up resister. (4) Schmitt Trigger input with pull-down
resistor.
PIN ASSIGNMENTS
PIN CONFIGURATION
ELECTROSTATIC
DISCHARGE SENSITIVITY
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
Power Supply Voltage ...................................................................... +6.5V
+V
+V
CC
to +V
DD
Difference ...................................................................
±
0.1V
Input Logic Voltage .................................................. –0.3V to (V
DD
+ 0.3V)
Input Current (except power supply) ...............................................
±
10mA
Power Dissipation .......................................................................... 750mW
Operating Temperature Range ......................................... –25
Operating Temperature Range ......................................... –25
°
C to +70
°
C
Storage Temperature ...................................................... –55
°
C to +125
°
C
Lead Temperature (soldering, 5s) ................................................. +260
°
C
(reflow, 10s) .................................................... +235
°
C
ABSOLUTE MAXIMUM RATINGS
LRCIN
DIN
BCKIN
CLKO
XTI
XTO
DGND
V
DD
HDCD
V
CC
2R
AGND2R
EXTR
V
OUT
R
AGND1
ML/I
2
S
MC/DEEM
MD/FSS
MUTE
MODE
CS/IWO
RST
ZERO
GAIN
V
CC
2L
AGND2L
EXTL
V
OUT
L
V
CC
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PCM1732U
Top View
SO-28
PACKAGE
SPECIFIED
DRAWING
TEMPERATURE
PACKAGE
ORDERING
TRANSPORT
PRODUCT
PACKAGE
NUMBER
(1)
RANGE
MARKING
NUMBER
(2)
MEDIA
PCM1732U
SO-28
217
–25
°
C to +70
°
C
PCM1732U
PCM1732U
Rails
"
"
"
"
"
PCM1732U/1K
Tape and Reel
NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/ ) are
available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces of “PCM1732U/1K” will get a single
1000-piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book.
available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces of “PCM1732U/1K” will get a single
1000-piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book.
PACKAGE/ORDERING INFORMATION
34
MCU Pin Arrangement and Functions
Pin Arrangement
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
P57
MCLK
MDATA
MLD
SENSE
FLOCK
TLOCK
SQCK
SUBQ
DMUTE
STAT
XRST
PUSW
CDRW
P6
1
P6
0
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
P2
1
P2
0
P8
7
P8
6
AMUTE
HDCD
P8
3
P8
2
P8
1
P8
0
POWER
DACRST
DAC.DATA
DAC.CLK
DAC.LD
V
CC
PB
1
/AN
1
PB
0
/AN
0
AV
SS
TEST
X
2
X
1
V
SS
OSC
1
OSC
2
RES
P9
0
OP_SW
CL_SW
MTR_CL
MTR_OP
S0S1
P2
2
VFD.DO
VFD.DI
VFD.CLK
VFD.LAT
P1
4
P1
5
P1
6
REMOTE
AV
CC
PB
7
/AN
7
PB
6
/AN
6
PB
5
/AN
5
PB
4
/AN
4
PB
3
/AN
3
PB
2
/AN
2
Figure 1.2 Pin Arrangement
HD755
35
Internal Block Diagram
Figure 1.1 shows a block diagram.
Port 8
P8
7
P8
6
/FTID
P8
5
/FTIC
P8
4
/FTIB
P8
3
/FTIA
P8
2
/FTOB
P8
1
/FTOA
P8
0
/FTCI
ROM
Port 7
P7
7
P7
6
/TMOV
P7
5
/TMCIV
P7
4
/TMRIV
P7
3
Port 6
P6
7
P6
6
P6
5
P6
4
P6
3
P6
2
P6
1
P6
0
CMOS large-
current port
I
current port
I
OL
= 10 mA
@V
OL
= 1V
P5
7
/
INT
7
P5
6
/
INT
6
/TMIB
P5
5
/
INT
5
/
ADTRG
P5
4
/
INT
4
P5
3
/
INT
3
P5
2
/
INT
2
P5
1
/
INT
1
P5
0
/
INT
0
Port 1
P1
0
/TMOW
P1
4
/PWM
P1
5
/
IRQ
1
P1
6
/
IRQ
2
P1
7
/
IRQ
3
/TRGV
Port 2
P2
0
/SCK
3
P2
1
/RXD
P2
2
/TXD
Port 3
P3
0
/SCK
1
P3
1
/SI
1
P3
2
/SO
1
P9
0
/FV
PP
*
P9
1
P9
2
P9
3
P9
4
Port 9
PB
0
/AN
0
PB
1
/AN
1
PB
2
/AN
2
PB
3
/AN
3
PB
4
/AN
4
PB
5
/AN
5
PB
6
/AN
6
PB
7
/AN
7
V
SS
V
CC
RES IRQ
0
TEST
OSC
1
OSC
2
X
1
X
2
CPU
H8/300L
Data bus (lower)
System clock
generator
Subclock
generator
RAM
Timer A
SCI1
Timer B1
Watchdog
timer
A/D converter
SCI3
Timer X
Timer V
14-bit PWM
AV
CC
AV
SS
Port 5
Port B
Data bus (upper)
Address bus
Figure 1.1 Block Diagram
HD755
36
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