Harman Kardon HD 755 (serv.man9) Service Manual ▷ View online
MN662790RAS1
Block Diagram
SERVO CPU
OUTPUT
PORT
MICROCOMPUTER
INTERFACE
DSL•PLL VCO
60
57
4
5
18
71
32
RST
TEST
FE
33
TE
34
RFENV
37
TRCRS
35
VDET
39
BDO
38
RFDET
36
OFT
DIGITAL
DEEMPHASIS
1 BIT DAC
LOGICS
8 TIMES
OVER SAMPLING
DIGITAL FILTER
EFM DEMODULATION
SYNC INTERPOLATION
SUBCODE DEMODULATION
CLV
SERVO
INTERPOLATION
SOFT MUTING
DIGITAL
ATTENUATION
PEAK DETECT
AUTO CUE
DIGITAL
AUDIO
INTERFACE
CIRC ERROR CORRECTION
DEINTERLEAVE
16K
SRAM
D/A
CONVERTER
29
V
REF
25
61
ECS
BYTCK/TRVSTOP
LDON
PLAY
FLOCK
TLOCK
40
42
11
12
26
KICK
21
TRV
16
DMUTE
1
BCLK
3
SRDATA
2
LRCK
23
PC
24
ECM
6
TX
64
IPFLAG
65
FLAG
22
TVD
27
TRD
28
FOD
31
TBAL
30
FBAL
43
WVEL
10
SENSE
STAT
X1
X2
MSEL
CSEL
PMCK
FCLK
SMCK
VCOF2
58
79
77
59
20
63
19
CK384/EFM
54
VCOF
49
MDATA
8
MCLK
7
MLD
9
17
44
46
45
47
41
52
76
78
78
RSEL
ARF
PSEL
DSLF
PLLF2
48
PLLF
62
13
67
66
55
56
68
15
14
80
CLDCK
BLKCK
SUBC
SBCK
FLAG6/RESY
69
DEMPH
CRC
CLVS
70
IOSEL
SRDATEIN/PSEL
BCLKIN/SSEL
LRCKIN/MSEL
EFM
53
PCK
SUBQ
SQCK
SSEL
I
REF
DRF
75
73
PWM
(L
)
PWM
(R
)
+
–
+
–
SUBCODE
BUFFER
51
50
AV
DD2
AV
SS2
OUTR
OUTL
74
72
72
A/D CONVERTER
INPUT PORT
SERVO
TIMING GENERATOR
TIMING GENERATOR
TIMING
GENERATOR
PITCH CONTROL
VCO
V
DD
V
SS
DV
DD1
DV
SS1
AV
DD1
AV
SS1
HD755
17
MN662790RAS1
Pin Descriptions
Pin No.
Symbol
I/O
Function Description
1
BCLK
O
SRDATA bit clock output.
2
LRCK
O
Left/right channel discrimination signal output.
3
SRDATA
O
Serial data output.
4
DV
DD1
I
Power supply for digital circuits.
5
DV
SS1
I
Ground for digital circuits.
6
TX
O
Digital audio interface output signal.
7
MCLK
I
Microcomputer command clock input. (Data is latched at rising edge.)
8
MDATA
I
Microcomputer command data input.
9
MLD
I
Microcomputer command load signal input.
"L" level: load.
10
SENSE
O
Sense signal output. (OFT, FESL, NACEND, NAJEND, SFG, and NWTEND)
11
FLOCK
O
During default operation, focus servo convergence signal.
"L" level: convergence.
During command execution, direction detection output for external track
counter.
12
TLOCK
O
During default operation, tracking servo convergence signal. "L" level:
convergence.
During command execution, traverse speed control output.
13
BLKCK
O
Subcode block clock signal (f
BLKCK
=75 Hz)
14
SQCK
I
External clock input for subcode Q register
15
SUBQ
O
Subcode Q data output
16
DMUTE
I
Muting input. (Effective only for an output bit rate of 64 f
s
) "H" level: muting.
17
STAT
O
Status signal.
(CRC, CLVS, TTSTOP, JCLVS, SQOK, FLAG6, SENSE, FLOCK,
TLOCK, rpm data, and FCLV)
18
RST
I
Reset input.
"L" level: reset.
19
SMCK
O
If MSEL is "H" level, 8.4672 MHz clock signal output.
If MSEL is "L" level, 4.2336 MHz clock signal output
20 CSEL O Oscillation frequency selection: "H" is 33.8688MHz; "L" is 16.9344MHz.
21
TRV
O
Traverse forced feed output.
(tristate)
22
TVD
O
Traverse drive output.
23
PC
O
Spindle motor ON signal.
"L" level: ON (default).
24
ECM
O
Spindle motor drive signal (forced mode output).
(tristate)
25
ECS
O
Spindle motor drive signal (servo error signal output).
(tristate)
26
KICK
O
Kick pulse output.
(tristate)
27
TRD
O
Tracking drive output.
28
FOD
O
Focus drive output.
29
V
REF
I
Reference voltage for DA output (TVD, ECS, TRD, FOD, FBAL, and
TBAL).
30
FBAL
O
Focus balance adjustment output.
31
TBAL
O
Tracking balance adjustment output.
32
FE
I
Focus error signal input. (analog input)
HD755
18
MN662790RAS1
Pin Descriptions (continued)
Pin No.
Symbol
I/O
Function Description
41
PLLF2
I/O
PLL loop filter characteristic selection pin.
42 TOFS O
Tracking offset adjustment or DSL balance output(D/A output).
43
WVEL
O
Double-speed status signal output.
"H" level: double-speed.
44
ARF
I
RF signal input.
45
I
REF
I
Reference current input pin.
46
DRF
I
DSL bias pin.
47
DSLF
I/O
DSL loop filter pin.
48
PLLF
I/O
PLL loop filter pin.
49
VCOF
I/O
VCO loop filter pin.
50
AV
DD2
I
Power supply for analog circuits (DSL, PLL, D/A converter output, and A/D
converter).
51
AV
SS2
I
Ground for analog circuits (DSL, PLL, D/A converter output, and A/D
converter).
52
EFM
O
EFM signal output. EFM output when IOSEL is "H" level.
or CK384
•
Crystal oscillator 16.9344-MHz clock output when I
•
OSEL is "L" level.
•
384 f
s
output from signal processing block. (During
variable-pitch operation, this is the VCO clock.)
Commands permit switching among the above three outputs.
53
PCK
O
PLL derived clock or DSL balance output. f
PCK
=4.3218 MHz.
or DSLB
54
VCOF2
I/O
VCO loop filter pin.
55
SUBC
O
Subcode serial output.
56
SBCK
I
Serial clock input for subcode serial output.
57
V
SS
I
Ground for oscillator circuit.
58
X1
I
Crystal oscillator circuit input/output pins. f=16.9344 MHz, 33.8688 MHz.
59
X2
O
Crystal oscillator circuit output/output pins. f=16.9344 MHz, 33.8688 MHz.
60
V
DD
I
Oscillator circuit power supply.
61
BYTCK or
O
When IOSEL is "H" level, byte clock signal output.
TRVSTOP
When IOSEL is "L" level, traverse stop signal output. "H" level: stop mode.
62
CLDCK
O
Subcode frame clock signal output pin. (f
CLDCK
=7.35 kHz)
63
FCLK
O
Crystal frame clock signal output. (f
FCLK
=7.35 kHz)
64
IPFLAG
O
Interpolation flag signal output. "H" level: interpolation.
65
FLAG
O
Flag signal output.
33
TE
I
Tracking error signal input.
(analog input)
34
RFENV
I
RF envelope signal input.
(analog input)
35
VDET
I
Vibration detection signal input.
"H" level: vibration detected.
36
OFT
I
Offtrack signal input.
"H" level: offtrack.
37
TRCRS
I
Track cross signal input.
(analog input)
38
RFDET
I
RF detection signal input.
"L" level: detected.
39
BDO
I
Dropout signal input.
"H" level: dropout.
40
LDON
O
Laser ON signal output.
"H" level: ON.
HD755
19
MN662790RAS1
66
CLVS
O
Spindle servo phase synchronization signal output. "H" level: CLV. "L"
level: rough servo.
67
CRC
O
During default operation, subcode CRC check result output. "H" level: OK.
"L" level: no good.
During command execution, pulse output for external track counter.
68
DEMPH
O
De-emphasis detection signal output. "H" level: ON.
69
FLAG6 or
O
When IOSEL is "L" level, FLAG6 output, signal for resetting address of
RESY
RAM for error correction de-interleave. "L" level: address reset.
When IOSEL is "H" level, RESY output, frame resynchronization signal.
"H" level: synchronized. "L" level: out of sync.
70
IOSEL
I
Mode selection pin
71
TEST
I
Test pin.
Keep this at "H" level.
72
AV
DD1
I
Power supply for analog circuits. (common use for left and right channel
audio outputs.)
73
OUTL
O
Left channel audio output.
74 AV
SS1
I Ground for analog circuits. (common use for left and right channel audio
outputs.)
75
OUTR
O
Right channel audio output.
76
RSEL
I
RF signal polarity selection pin.
"H" level: bright level is "H."
"L" level: bright level is "L."
77 V
CC5V
I
5-V power supply applied to pins for 5-V input.
78
PSEL
I
When IOSEL is "H" level, test pin.
Keep this at "L" level.
When IOSEL is "L" level, SRDATA input.
79
MSEL
I
When IOSEL is "H" level, frequency selection pin for SMCK pin output.
"H" level: SMCK=8.4672 MHz
When IOSEL is "L" level, LRCK input.
"H" level: left channel data.
"L" level: right channel data.
SMCK output fixed at 4.2336 MHz.
80
SSEL
I
When IOSEL is "H" level, SUBQ pin output mode selection pin.
"H" level: buffered subcode Q mode.
"L" level: CLDCK synchronization mode.
When IOSEL is "L" level, BCKL input.
Buffered subcode Q mode.
Pin Descriptions (continued)
Pin No. Symbol I/O Function Description
HD755
20
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