Harman Kardon AVR 350 (serv.man5) Service Manual ▷ View online
ADV7322
Preliminary Technical Data
Rev. PrA | Page 18 of 88
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
64
GND_
IO
63
CLKIN_
B
62
S7
61
S6
60
S5
59
S4
58
S3
57
DGND
56
V
DD
55
S2
54
S1
53
S0
52
TEST5
51
TEST4
50
S_HSYNC
49
S_VSYNC
47
R
SET1
46
V
REF
45
COMP1
42
DAC C
43
DAC B
44
DAC A
48
S_BLANK
41
V
AA
40
AGND
39
DAC D
37
DAC F
36
COMP2
35
R
SET2
34
EXT_LF
33
RESET
38
DAC E
2
TEST0
3
TEST1
4
Y0
7
Y3
6
Y2
5
Y1
1
V
DD_IO
8
Y4
9
Y5
10
V
DD
12
Y6
13
Y7
14
TEST2
15
TEST3
16
C0
11
DGND
17
C1
18
C2
19
I
2
C
20
ALSB
21
SDA
22
SCLK
23
P_HSYNC
24
P_VSYNC
25
P_
BLANK
26
C3
27
C4
28
C5
29
C6
30
C7
31
RTC_
SCR_
TR
32
CLKIN_
A
PIN 1
ADV7322
TOP VIEW
(Not to Scale)
05067-
019
Figure 19. Pin Configuration
harman/kardon
AVR 347/230, AVR 350/230 Semiconductor Pinouts
Page 9 of 51
Preliminary Technical Data
ADV7322
Rev. PrA | Page 19 of 88
Table 6. Pin Function Descriptions
Mnemonic
Input/Output Function
DGND
G
Digital Ground.
AGND
G
Analog Ground.
CLKIN_A
I
Pixel Clock Input for HD (74.25 MHz Only, PS Only (27 MHz), SD Only (27 MHz).
CLKIN_B
I
Pixel Clock Input. Requires a 27 MHz reference clock for progressive scan mode or a 74.25 MHz (74.1758
MHz) reference clock in HDTV mode. This clock is only used in dual modes.
MHz) reference clock in HDTV mode. This clock is only used in dual modes.
COMP1,
COMP2
COMP2
O
Compensation Pin for DACs. Connect 0.1 µF capacitor from COMP pin to V
AA
.
DAC A
O
CVBS/Green/Y/Y Analog Output.
DAC B
O
Chroma/Blue/U/Pb Analog Output.
DAC C
O
Luma/Red/V/Pr Analog Output.
DAC D
O
In SD Only Mode: CVBS/Green/Y Analog Output; in HD Only Mode and Simultaneous HD/SD Mode:
Y/Green [HD] Analog Output.
Y/Green [HD] Analog Output.
DAC E
O
In SD Only Mode: Luma/Blue/U Analog Output; in HD Only Mode and Simultaneous HD/SD Mode: Pr/Red
Analog Output.
Analog Output.
DAC F
O
In SD Only Mode: Chroma/Red/V Analog Output; in HD Only Mode and Simultaneous HD/SD Mode:
Pb/Blue [HD] Analog Output.
Pb/Blue [HD] Analog Output.
P_HSYNC
I
Video Horizontal Sync Control Signal for HD in Simultaneous SD/HD Mode and HD Only Mode.
P_VSYNC
I
Video Vertical Sync Control Signal for HD in Simultaneous SD/HD Mode and HD Only Mode.
P_BLANK
I
Video Blanking Control Signal for HD in Simultaneous SD/HD Mode and HD Only Mode.
S_BLANK
I/O
Video Blanking Control Signal for SD Only.
S_HSYNC
I/O
Video Horizontal Sync Control Signal for SD Only.
S_VSYNC
I/O
Video Vertical Sync Control Signal for SD Only.
Y7 to Y0
I
SD or Progressive Scan/HDTV Input Port for Y Data. Input port for interleaved progressive scan data. The
LSB is set up on Pin Y0.
LSB is set up on Pin Y0.
C7 to C0
I
Progressive Scan/HDTV Input Port 4:4:4 Input Mode. This port is used for the Cb [Blue/U] data. The LSB is
set up on Pin C0.
set up on Pin C0.
S7 to S0
I
SD or Progressive Scan/HDTV Input Port for Cr [Red/V] data in 4:4:4 input mode. LSB is set up on Pin S0.
RESET
I
This input resets the on-chip timing generator and sets the ADV7322 into default register setting. RESET is
an active low signal.
an active low signal.
R
SET1
, R
SET2
I
A 3040 Ω resistor must be connected from this pin to AGND and is used to control the amplitudes of the
DAC outputs.
DAC outputs.
SCLK
I
I
2
C Port Serial Interface Clock Input.
SDA
I/O
I
2
C Port Serial Data Input/Output.
ALSB
I
TTL Address Input. This signal sets up the LSB of the I
2
C address. When this pin is tied low, the I
2
C filter is
activated, which reduces noise on the I
2
C interface.
V
DD_IO
P
Power Supply for Digital Inputs and Outputs.
V
DD
P
Digital Power Supply.
V
AA
P
Analog Power Supply.
V
REF
I/O
Optional External Voltage Reference Input for DACs or Voltage Reference Output (1.235 V).
EXT_LF
I
External Loop Filter for the Internal PLL.
RTC_SCR_TR I
Multifunctional Input. Real time control (RTC) input, timing reset input, subcarrier reset input.
I
2
C
I
This input pin must be tied high (V
DD_IO
) for the ADV7322 to interface over the I
2
C port.
GND_IO
Digital Input/Output Ground.
TEST0 to
TEST5
TEST5
I
Not used. Tie to DGND
harman/kardon
AVR 347/230, AVR 350/230 Semiconductor Pinouts
Page 10 of 51
1
Features
•
Low-voltage and Standard-voltage Operation
– 2.7 (V
CC
= 2.7V to 5.5V)
– 1.8 (V
CC
= 1.8V to 5.5V)
•
Internally Organized 128 x 8 (1K), 256 x 8 (2K), 512 x 8 (4K),
1024 x 8 (8K) or 2048 x 8 (16K)
1024 x 8 (8K) or 2048 x 8 (16K)
•
Two-wire Serial Interface
•
Schmitt Trigger, Filtered Inputs for Noise Suppression
•
Bidirectional Data Transfer Protocol
•
100 kHz (1.8V) and 400 kHz (2.7V, 5V) Compatibility
•
Write Protect Pin for Hardware Data Protection
•
8-byte Page (1K, 2K), 16-byte Page (4K, 8K, 16K) Write Modes
•
Partial Page Writes Allowed
•
Self-timed Write Cycle (5 ms max)
•
High-reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
– Data Retention: 100 Years
•
Automotive Grade and Lead-free/Halogen-free Devices Available
•
8-lead PDIP, 8-lead JEDEC SOIC, 8-lead MAP, 5-lead SOT23,
8-lead TSSOP and 8-ball dBGA2 Packages
8-lead TSSOP and 8-ball dBGA2 Packages
•
Die Sales: Wafer Form, Waffle Pack and Bumped Wafers
Description
The AT24C01A/02/04/08A/16A provides 1024/2048/4096/8192/16384 bits of serial
electrically erasable and programmable read-only memory (EEPROM) organized as
128/256/512/1024/2048 words of 8 bits each. The device is optimized for use in many
industrial and commercial applications where low-power and low-voltage operation
are essential. The AT24C01A/02/04/08A/16A is available in space-saving 8-lead PDIP,
8-lead JEDEC SOIC, 8-lead MAP, 5-lead SOT23 (AT24C01A/AT24C02/AT24C04), 8-
lead TSSOP, and 8-ball dBGA2 packages and is accessed via a Two-wire serial inter-
face. In addition, the entire family is available in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to
5.5V) versions.
electrically erasable and programmable read-only memory (EEPROM) organized as
128/256/512/1024/2048 words of 8 bits each. The device is optimized for use in many
industrial and commercial applications where low-power and low-voltage operation
are essential. The AT24C01A/02/04/08A/16A is available in space-saving 8-lead PDIP,
8-lead JEDEC SOIC, 8-lead MAP, 5-lead SOT23 (AT24C01A/AT24C02/AT24C04), 8-
lead TSSOP, and 8-ball dBGA2 packages and is accessed via a Two-wire serial inter-
face. In addition, the entire family is available in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to
5.5V) versions.
Table 1. Pin Configuration
Pin Name
Function
A0 - A2
Address Inputs
SDA
Serial Data
SCL
Serial Clock Input
WP
Write Protect
NC
No Connect
GND
Ground
VCC
Power Supply
Two-wire
Serial EEPROM
Serial EEPROM
1K (128 x 8)
2K (256 x 8)
4K (512 x 8)
8K (1024 x 8)
16K (2048 x 8)
AT24C01A
AT24C02
AT24C04
AT24C08A
AT24C16A
AT24C02
AT24C04
AT24C08A
AT24C16A
0180V–SEEPR–8/05
8-lead SOIC
1
2
3
4
8
7
6
5
A0
A1
A2
GND
VCC
WP
SCL
SDA
8-lead PDIP
1
2
3
4
8
7
6
5
A0
A1
A2
GND
VCC
WP
SCL
SDA
8-lead MAP
Bottom View
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
A0
A1
A2
GND
5-lead SOT23
1
2
3
5
4
SCL
GND
SDA
WP
VCC
8-ball dBGA2
Bottom View
VCC
WP
SCL
SDA
A0
A1
A2
GND
1
2
3
4
8
7
6
5
8-lead TSSOP
1
2
3
4
8
7
6
5
A0
A1
A2
GND
VCC
WP
SCL
SDA
harman/kardon
AVR 347/230, AVR 350/230 Semiconductor Pinouts
Page 11 of 51
CS42528
2. PIN DESCRIPTIONS
Pin Name
#
Pin Description
CX_SDIN1
CX_SDIN2
CX_SDIN3
CX_SDIN4
CX_SDIN2
CX_SDIN3
CX_SDIN4
1
64
63
62
Codec Serial Audio Data Input
(Input) - Input for two’s complement serial audio data.
CX_SCLK
2
CODEC Serial Clock
(Input/Output) - Serial clock for the CODEC serial audio interface.
CX_LRCK
3
CODEC Left Right Clock
(Input/Output) - Determines which channel, Left or Right, is currently active on
the CODEC serial audio data line.
VD
4
51
Digital Power
(Input) - Positive power supply for the digital section.
DGND
5
52
Digital Ground
(Input) - Ground reference. Should be connected to digital ground.
VLC
6
Control Port Power
(Input) - Determines the required signal level for the control port.
SCL/CCLK
7
Serial Control Port Clock
(Input) - Serial clock for the serial control port. Requires an external pull-up
resistor to the logic interface voltage in I
2
C mode as shown in the Typical Connection Diagram.
SDA/CDOUT
8
Serial Control Data
(Input/Output) - SDA is a data I/O line in I
2
C mode and requires an external pull-up
resistor to the logic interface voltage, as shown in the Typical Connection Diagram. CDOUT is the output
data line for the control port interface in SPI mode.
AD1/CDIN
9
Address Bit 1 (I
2
C)/Serial Control Data (SPI)
(Input) - AD1 is a chip address pin in I
2
C mode; CDIN is
the input data line for the control port interface in SPI mode.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
CX_SDIN1
SAI
_SC
LK
SAI
_L
R
C
K
VD
DGND
VLC
SCL/CCLK
SDA/CDOUT
AD1/CDIN
AD0/CS
INT
RST
AINR-
AINR+
AINL+
AINL-
VQ
FI
LT
+
RE
F
G
ND
AO
U
T
B
4-
AO
U
T
B
4+
AO
U
T
A
4+
AO
UT
A
4-
VA
AG
N
D
AO
U
T
B
3-
AO
U
T
B3
+
AO
U
T
A3
+
AO
U
T
A
3-
AO
UT
B
2-
AO
U
T
B2
+
AO
U
T
A2
+
AOUTA2-
AOUTB1-
AOUTB1+
AOUTA1+
AOUTA1-
MUTEC
AGND
VARX
RXP7/GPO7
RXP6/GPO6
RXP5/GPO5
RXP4/GPO4
RXP3/GPO3
RXP2/GPO2
RXP1/GPO1
LPFLT
RX
P
0
TXP
VD
DG
ND
VL
S
SAI
_SD
O
U
T
RM
CK
CX
_S
DO
UT
A
D
CI
N2
A
D
CI
N1
OMC
K
CX_LRCK
CX_SCLK
CX
_S
DI
N4
CX
_S
DI
N3
C
X
_S
DI
N2
CS42528
harman/kardon
AVR 347/230, AVR 350/230 Semiconductor Pinouts
Page 12 of 51
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