Harman Kardon AVR 350 (serv.man5) Service Manual ▷ View online
CS42528
10 Address Bit 0 (I
2
C)/Control Port Chip Select (SPI) (Input
) - AD0 is a chip address pin in I
2
C mode; CS
is the chip select signal in SPI mode.
INT
11 Interrupt (Output) - The CS42528 will generate an interrupt condition as per the Interrupt Mask register.
See “Interrupts” on page 40 for more details.
RST
12 Reset (Input) - The device enters a low power mode and all internal registers are reset to their default
settings when low.
AINR-
AINR+
AINR+
13
14
Differential Right Channel Analog Input
(Input) - Signals are presented differentially to the delta-sigma
modulators via the AINR+/- pins.
AINL+
AINL-
AINL-
15
16
Differential Left Channel Analog Input
(Input) - Signals are presented differentially to the delta-sigma
modulators via the AINL+/- pins.
VQ
17 Quiescent Voltage (Output) - Filter connection for internal quiescent reference voltage.
FILT+
18 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.
REFGND
19 Reference Ground (Input) - Ground reference for the internal sampling circuits.
AOUTA1 +,-
AOUTB1 +,-
AOUTA2 +,-
AOUTB2 +,-
AOUTA3 +,-
AOUTB3 +,-
AOUTA4 +,-
AOUTB4 +,-
AOUTB1 +,-
AOUTA2 +,-
AOUTB2 +,-
AOUTA3 +,-
AOUTB3 +,-
AOUTA4 +,-
AOUTB4 +,-
36,37
35,34
32,33
31,30
28,29
27,26
22,23
21,20
Differential Analog Output
(Output) - The full-scale differential analog output level is specified in the
Analog Characteristics specification table.
VA
VARX
VARX
24
41
Analog Power
(Input) - Positive power supply for the analog section.
AGND
25
40
Analog Ground
(Input) - Ground reference. Should be connected to analog ground.
MUTEC
38 Mute Control (Output) - The Mute Control pin outputs high impedance following an initial power-on con-
dition or whenever the PDN bit is set to a ‘1’, forcing the codec into power-down mode. The signal will
remain in a high impedance state as long as the part is in power-down mode. The Mute Control pin goes
to the selected “active” state during reset, muting, or if the master clock to left/right clock frequency ratio
is incorrect. This pin is intended to be used as a control for external mute circuits to prevent the clicks
and pops that can occur in any single supply system. The use of external mute circuits are not manda-
tory but may be desired for designs requiring the absolute minimum in extraneous clicks and pops.
LPFLT
39 PLL Loop Filter (Output) - An RC network should be connected between this pin and ground.
RXP7/GPO7
RXP6/GPO6
RXP5/GPO5
RXP4/GPO4
RXP3/GPO3
RXP2/GPO2
RXP1/GPO1
RXP6/GPO6
RXP5/GPO5
RXP4/GPO4
RXP3/GPO3
RXP2/GPO2
RXP1/GPO1
42
43
44
45
46
47
48
S/PDIF Receiver Input/ General Purpose Output
(Input/Output) - Receiver inputs for S/PDIF encoded
data. The CS42528 has an internal 8:2 multiplexer to select the active receiver port, according to the
Receiver Mode Control 2 register. These pins can also be configured as general purpose output pins,
ADC Overflow indicators or Mute Control outputs according to the RXP/General Purpose Pin Control
registers.
RXP0
49 S/PDIF Receiver Input (Input) - Dedicated receiver input for S/PDIF encoded data.
TXP
50 S/PDIF Transmitter Output (Output) - S/PDIF encoded data output, mapped directly from one of the
receiver inputs as indicated by the Receiver Mode Control 2 register.
VLS
53 Serial Port Interface Power (Input) - Determines the required signal level for the serial port interfaces.
SAI_SDOUT
54 Serial Audio Interface Serial Data Output (Output) - Output for two’s complement serial audio PCM
data from the S/PDIF incoming stream. This pin can also be configured to transmit the output of the inter-
nal and external ADCs.
RMCK
55 Recovered Master Clock (Output) - Recovered master clock output from the External Clock Reference
(OMCK, pin 59) or the PLL which is locked to the incoming S/PDIF stream or CX_LRCK.
harman/kardon
AVR 347/230, AVR 350/230 Semiconductor Pinouts
Page 13 of 51
CS42528
CX_SDOUT
56 CODEC Serial Data Output (Output) - Output for two’s complement serial audio data from the internal
and external ADCs.
ADCIN1
ADCIN2
ADCIN2
58
57
External ADC Serial Input
(Input) - The CS42528 provides for up to two external stereo analog to digital
converter inputs to provide a maximum of six channels on one serial data output line when the CS42528
is placed in One Line mode.
OMCK
59 External Reference Clock (Input) - External clock reference that must be within the ranges specified in
the register “OMCK Frequency (OMCK Freqx)” on page 54.
SAI_LRCK
60 Serial Audio Interface Left/Right Clock (Input/Output) - Determines which channel, Left or Right, is
currently active on the serial audio data line.
SAI_SCLK
61 Serial Audio Interface Serial Clock (Input/Output) - Serial clock for the Serial Audio Interface.
harman/kardon
AVR 347/230, AVR 350/230 Semiconductor Pinouts
Page 14 of 51
CS42528
20
DS586PP5
3. TYPICAL CONNECTION DIAGRAM
V D
AO UTA1+
24
0.1 µF +
10 µF
100 µF
0.1 µF
+
+
17
18
VQ
FILT+
36
37
37
0.1 µF
4.7 µF
VA
+
10 µF
51
AO UTA1-
AO UTB1+
35
34
34
AO UTB1-
AO UTA2+
32
33
33
AO UTA2-
AO UTB2+ 31
30
AO UTB2-
AO UTA3+ 28
29
AO UTA3-
AO UTB3+ 27
26
AO UTB3-
AO UTA4+
22
23
23
AO UTA4-
AO UTB4+
21
20
20
AO UTB4-
M UTEC
38
25
DG ND DG ND
5
RE FG ND 19
41
4
VA
VD
0.1 µF
AG ND
A G ND
52
40
LPFLT
39
AINL+
AINL-
AINR+
AINR-
15
16
14
13
Connect D G ND and A G ND at single point near C odec
0.01 µF
0.1 µF +
10 µF
+5 V
0.01 µF
0.01 µF
+3.3 V to +5 V
+
10 µF
0.1 µF
0.01 µF
VLS
0.1 µF
+2.5 V
to +5 V
53
V LC
0.1 µF
+1.8 V
to +5 V
6
3
60
59
62
1
64
61
2
63
8
7
SCL/CCLK
SDA/CDO UT
SDA/CDO UT
A D1/CDIN
RS T
12
9
O M CK
CX_SDIN1
SA I_LRCK
SAI_SCLK
CX_SDIN3
CX _S DIN2
CX _S DIN4
CX_LRCK
CX_SCLK
A D0/CS
10
INT
11
Digital A udio
P rocessor
M icro-
Controller
55
RM CK
58
A DCIN1
57
A DCIN2
CS5361
A/D Converter
CS5361
A /D Converter
56
CX_SDO UT
54
SAI_SDO UT
48
46
49
44
45
47
RX P0
RXP1/G PO 1
RXP1/G PO 1
S/PDIF
Interface
50
TXP
Driver
Up to 8
Sources
43
RXP2/G PO 2
RXP3/G PO 3
RXP4/G PO 4
RXP5/G PO 5
RXP6/G PO 6
RXP7/G PO 7
RXP3/G PO 3
RXP4/G PO 4
RXP5/G PO 5
RXP6/G PO 6
RXP7/G PO 7
42
O SC
Analog O utput Buffer
2
and
M ute Circuit (optional)
Analog Output B uffer
2
and
M ute Circuit (optional)
Analog O utput Buffer
2
and
M ute Circuit (optional)
Analog Output B uffer
2
and
M ute Circuit (optional)
Analog O utput Buffer
2
and
M ute Circuit (optional)
Analog Output B uffer
2
and
M ute Circuit (optional)
Analog O utput Buffer
2
and
M ute Circuit (optional)
Analog O utput Buffer
2
and
M ute Circuit (optional)
M ute
Drive
(optional)
+VA
*
* Pull up or down as
required on startup if the
M ute C ontrol is used.
*
2700 pF*
2700 pF*
Left A nalog Input
Right Analog Inpu
Analog
Input
B uffer
1
Analog
Input
B uffer
1
CFILT
3
RFILT
3
CRIP
3
2 kΩ
2 kΩ
**
**
** Resistors are required for
I
2
C control port operation
1. See the ADC Input Filter section in the Appendix.
2. See the DAC O utput Filter section in the Appendix.
3. See the PLL Filter section in the Appendix.
2. See the DAC O utput Filter section in the Appendix.
3. See the PLL Filter section in the Appendix.
Figure 5. Typical Connection Diagram
CS42528
harman/kardon
AVR 347/230, AVR 350/230 Semiconductor Pinouts
Page 15 of 51
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AVR 347/230, AVR 350/230 Semiconductor Pinouts
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