Harman Kardon AVR 350 (serv.man5) Service Manual ▷ View online
Data Sheet
8 Mbit SPI Serial Flash
SST25VF080B
SST25VF080B
3
©2006 Silicon Storage Technology, Inc.
S71296-01-000
1/06
PIN DESCRIPTION
FIGURE 1: P
IN
A
SSIGNMENTS
TABLE
1: P
IN
D
ESCRIPTION
Symbol
Pin Name
Functions
SCK
Serial Clock
To provide the timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the clock input,
while output data is shifted out on the falling edge of the clock input.
Commands, addresses, or input data are latched on the rising edge of the clock input,
while output data is shifted out on the falling edge of the clock input.
SI
Serial Data Input
To transfer commands, addresses, or data serially into the device.
Inputs are latched on the rising edge of the serial clock.
Inputs are latched on the rising edge of the serial clock.
SO
Serial Data Output
To transfer data serially out of the device.
Data is shifted out on the falling edge of the serial clock.
Outputs Flash busy status during AAI Programming when reconfigured as RY/BY# pin.
See “Hardware End-of-Write Detection” on page 12 for details.
Data is shifted out on the falling edge of the serial clock.
Outputs Flash busy status during AAI Programming when reconfigured as RY/BY# pin.
See “Hardware End-of-Write Detection” on page 12 for details.
CE#
Chip Enable
The device is enabled by a high to low transition on CE#. CE# must remain low for the
duration of any command sequence.
duration of any command sequence.
WP#
Write Protect
The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register.
HOLD#
Hold
To temporarily stop serial communication with SPI flash memory without resetting the
device.
device.
V
DD
Power Supply
To provide power supply voltage: 2.7-3.6V for SST25VF080B
V
SS
Ground
T1.0 1296
1
2
3
4
8
7
6
5
CE#
SO
WP#
VSS
VDD
HOLD#
SCK
SI
Top View
1296 08-soic S2A P1.0
1
2
3
4
8
7
6
5
CE#
SO
WP#
VSS
Top View
VDD
HOLD#
SCK
SI
1296 08-wson QA P2.0
8-
LEAD
SOIC
8-
CONTACT
WSON
harman/kardon
AVR 347/230, AVR 350/230 Semiconductor Pinouts
Page 45 of 51
PIN CONFIGURATION
PIN DESCRIPTION
PIN No
SYMBOL
NAME AND F UNCTION
1
C
1
+
Positive Terminal for the first Charge Pump Capacitor
2
V+
Doubled Voltage Terminal
3
C
1
-
Negative Terminal for the first Charge Pump Capacitor
4
C
2
+
Positive Terminal for the second Charge Pump Capacitor
5
C
2
-
Negative Terminal for the second Charge Pump Capacitor
6
V-
Inverted Voltage Terminal
7
T2
OUT
Second Transmitter Output Voltage
8
R2
IN
Second Receiver Input Voltage
9
R2
OUT
Second Receiver Output Voltage
10
T2
IN
Second Transmitter Input Voltage
11
T1
IN
First Transmitter Input Voltage
12
R1
OUT
First Receiver Output Voltage
13
R1
IN
First Receiver Input Voltage
14
T1
OUT
First Transmitter Output Voltage
15
GND
Ground
16
V
CC
Supply Voltage
ST202E/ST232E
2/12
harman/kardon
AVR 347/230, AVR 350/230 Semiconductor Pinouts
Page 46 of 51
harman/kardon
AVR 347/230, AVR 350/230 Semiconductor Pinouts
Page 47 of 51
TC7MZ4051,4052,4053FK
2001-10-23
2
Pin Assignment
(top view)
Truth Table
Control Inputs
“ON” Channel
Inhibit C* B A
MZ4051FK
MZ4052FK
MZ4053FK
L L L L 0 0X,
0Y
0X,
0Y,
0Z
L
L
L
H
1
1X, 1Y
1X, 0Y, 0Z
L
L
H
L
2
2X, 2Y
0X, 1Y, 0Z
L
L
H
H
3
3X, 3Y
1X, 1Y, 0Z
L H L L 4
¾
0X, 0Y, 1Z
L H L H 5
¾
1X, 0Y, 1Z
L H H L 6
¾
0X, 1Y, 1Z
L H H H 7
¾
1X, 1Y, 1Z
H X X X None None None
X: Don't care, *: Except MZ4052FK
1
14
0
3
A
B
C
13
12
11
10
9
15
4 1
2
3
4
5
6
7
6
COM
7
5
INH
V
EE
2
8
16
GND
V
CC
TC7MZ4051FK
1X
14
X-COM
0X
3X
A
B
13
12
11
10
9
15
0Y 1
2
3
4
5
6
7
2Y
Y-COM
3Y
1Y
INH
V
EE
2X
8
16
GND
V
CC
TC7MZ4052FK
X-COM
14
1X
0X
A
B
C
13
12
11
10
9
15
1Y 1
2
3
4
5
6
7
0Y
1Z
Z-COM
0Z
INH
V
EE
Y-COM
8
16
GND
V
CC
TC7MZ4053FK
harman/kardon
AVR 347/230, AVR 350/230 Semiconductor Pinouts
Page 48 of 51
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