Harman Kardon AVR 171S (serv.man4) Service Manual ▷ View online
W9825G6JH
Publication Release Date: Nov. 29, 2011
- 5 -
Revision A04
5. PIN
DESCRIPTION
PIN NUMBER
PIN NAME
FUNCTION
DESCRIPTION
23
26, 22,
29
36
A0
A12
Address
Multiplexed pins for row and column address.
Row address: A0
Row address: A0
A12. Column address: A0A8.
20, 21
BS0, BS1
Bank Select
Select bank to activate during row address latch time, or
bank to read/write during address latch time.
bank to read/write during address latch time.
2, 4, 5, 7, 8, 10,
11, 13, 42, 44,
45, 47, 48, 50,
45, 47, 48, 50,
51, 53
DQ0
DQ15
Data
Input/Output
Multiplexed pins for data output and input.
19
CS
Chip Select
Disable or enable the command decoder. When
command decoder is disabled, new command is
ignored and previous operation continues.
command decoder is disabled, new command is
ignored and previous operation continues.
18
RAS
Row Address
Strobe
Command input. When sampled at the rising edge of
the clock, RAS , CAS and WE define the operation
to be executed.
the clock, RAS , CAS and WE define the operation
to be executed.
17
CAS
Column
Address
Strobe
Referred to RAS
16
WE
Write Enable Referred to RAS
15, 39
LDQM,
UDQM
Input/Output
Mask
The output buffer is placed at Hi-Z(with latency of 2)
when DQM is sampled high in read cycle. In write
cycle, sampling DQM high will block the write operation
with zero latency.
when DQM is sampled high in read cycle. In write
cycle, sampling DQM high will block the write operation
with zero latency.
38 CLK
Clock Inputs
System clock used to sample inputs on the rising edge
of clock.
of clock.
37 CKE
Clock Enable
CKE controls the clock activation and deactivation.
When CKE is low, Power Down mode, Suspend mode,
or Self Refresh mode is entered.
When CKE is low, Power Down mode, Suspend mode,
or Self Refresh mode is entered.
1, 14, 27
V
DD
Power (+3.3V) Power for input buffers and logic circuit inside DRAM.
28, 41, 54
V
SS
Ground
Ground for input buffers and logic circuit inside DRAM.
3, 9, 43, 49
V
DDQ
Power (+3.3V)
for I/O Buffer
Separated power from V
DD
, to improve DQ noise
immunity.
6, 12, 46, 52
V
SSQ
Ground
for I/O Buffer
Separated ground from V
SS
, to improve DQ noise
immunity.
40
NC
No Connection No connection.
Harman Kardon
AVR 171 Service Manual
Page 121 of 174
©
1996
DATA SHEET
MOS FIELD EFFECT TRANSISTOR
μ
PA672T
N-CHANNEL MOS FET ARRAY
FOR SWITCHING
The
μPA672T is a super-mini-mold device provided
with two MOS FET elements. It achieves high-density
mounting and saves mounting costs.
mounting and saves mounting costs.
FEATURES
• Two MOS FET circuits in package the same size as
SC-70
• Automatic mounting supported
ABSOLUTE MAXIMUM RATINGS (T
A
= 25 ˚C)
PARAMETER
SYMBOL
TEST CONDITIONS
RATINGS
UNIT
Drain to Source Voltage
V
DSS
50
V
Gate to Source Voltage
V
GSS
±7.0
V
Drain Current (DC)
I
D(DC)
100
mA
Drain Current (pulse)
I
D(pulse)
PW
≤ 10 ms, Duty Cycle ≤ 50 %
200
mA
Total Power Dissipation
P
T
200 (Total)
mW
Channel Temperature
T
ch
150
˚C
Storage Temperature
T
stg
–55 to +150
˚C
Document No. G11259EJ1V0DS00 (1st edition)
Date Published June 1996 P
Printed in Japan
Date Published June 1996 P
Printed in Japan
PACKAGE DIMENSIONS (in millimeters)
0.2
+0.1
–0
0.15
+0.1
–0.05
2.1 ±
0.1
1.25 ±
0.1
0.65
1.3
0.7
2.0 ±0.2
0.9 ±0.1
0 to 0.1
0.65
6
1
5
2
4
3
PIN CONNECTION
6
5
4
1
2
3
1.
2.
3.
4.
5.
6.
Marking: MA
2.
3.
4.
5.
6.
Marking: MA
Source 1
Gate 1
Drain 2
Source 2
Gate 2
Drain 1
Gate 1
Drain 2
Source 2
Gate 2
Drain 1
(S1)
(G1)
(D2)
(S2)
(G2)
(D1)
(G1)
(D2)
(S2)
(G2)
(D1)
Harman Kardon
AVR 171 Service Manual
Page 122 of 174
Harman Kardon
AVR 171 Service Manual
Page 123 of 174
Harman Kardon
AVR 171 Service Manual
Page 124 of 174
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