Sony KV-32HS20 Service Manual ▷ View online
KV-32HS20/36HS20/36HS20H/32XBR450/36XBR450/36XBR450H
— 33 —
Control Register
Function & Link
Data
Type
Data
Range
Comment
Full
Vcomp1
Vcomp2
0
HCNT
HC_PARA_DC: Horizontal center
Adj. 0~(31)~63
1
HPOS H_POSITION: Horizontal position
Adj. 0~(31)~63
31
[Adj.-6steps]
2
HSIZ
H_SIZE: Horizontal size
Adj. 0~(31)~63
3
SLIN
MP_PARA_DC: Horizontal S-correction
Adj.
0~15
4
MPIN
MP_PARA_AMP: Horizontal middle pin
0~15
5
PIN
PIN_AMP: Horizontal pin
Adj. 0~(31)~63
6
UCP
UP_CPIN: Upper corner pin
Adj. 0~(31)~63
7
LCP
LO_CPIN: Lower corner pin
Adj. 0~(31)~63
8
UXCG UP_UCG: Upper extra corner pin gain
0~3
9
LXCG
LO_UCG: Lower extra corner pin gain
0~3
10
UXCP
UP_UCP: Upper extra corner pin position
0~3
11
LXCP
LO_UCP: Lower extra corner pin postion
0~3
12
XCPP
UC_POL: Extra corner pin polarity
0, 1
13
PPHA
PIN_PHASE: Pin phase
Adj. 0~(31)~63
14
VANG AFC_ANGLE: AFC angle
Adj. 0~(31)~63
15
LANG HC_PARA_PHASE: Linearity angle
Adj. 0~(31)~63
16 VBOW AFC_BOW: AFC bow
Adj. 0~(31)~63
17 LBOW HC_PARA_AMP: Linearity bow
Adj. 0~(31)~63
18
CPY1
Copy Function 1: (Set CPY1=1, then press MUTE + Enter.)
Copy all CXA2150D-2 data for Full mode to Vcomp1&2
Copy all CXA2150D-2 data for Full mode to Vcomp1&2
Micro
0, 1
For engineering design use only
38 [38]
42 [42]
42 [42]
15 [15]
31 [31]
31 [31]
2
Full: 480p/960i (4x3) display
Vcomp1: 480p/960i (16x9) display
Vcomp2: 1080i (16x9) display
Vcomp1: 480p/960i (16x9) display
Vcomp2: 1080i (16x9) display
( ): Settings at center
Adj.: Adjusted data
[Adj.-6steps]:
The adj. data for Vcomp2 mode
= The adj. data for Full/Vcomp1
modes - 6 steps
[Adj.-6steps]:
The adj. data for Vcomp2 mode
= The adj. data for Full/Vcomp1
modes - 6 steps
9
(32V)
or 7
(36V)
35 [35]
2
(32V)
or 1
(36V)
31 [31]
31 [31]
Device Name: CXA2150AQ { CRT Driver / SONY } / IC201 (A-board) / P/N: 8-752-093-35 (SBorSD#: NA)
Slave Address: 86h
Slave Address: 86h
31
[31]
Note:
The same CXA2150 service data is used for DX1A-2001&2000.
The same CXA2150 service data is used for DX1A-2001&2000.
2
0
0
31 [31]
2
45 [45]
3 [3]
Data Initial Settings & [Average Data]
(32V&36V CRTs)
Register
No & Name
Data
(32Vor36V)
:
The data for 36V are used as the
Initial & CBA data.
Initial & CBA data.
From the system micro (V 2.0),
the deflection control-related
initial settings are the same as
their average data.
the deflection control-related
initial settings are the same as
their average data.
DX1A-2001&2000 SERVICE LIST (#4-2):
CXA2150D-2 {Deflection Controls: D2}
0
31 [31]
KV-32HS20/36HS20/36HS20H/32XBR450/36XBR450/36XBR450H
— 34 —
Control Register
Function & Link
Data
Type
Data
Range
Comment
Full
Vcomp1
Vcomp2
0
HBLK
HBLK_SW: Horizontal blanking switch
0, 1
1
LBLK
LEFT_BLK: Left blanking
0~63
50
2
RBLK
RIGHT_BLK: Right blanking
0~63
27
3
VBLK
VBLK_SW: Vertical blanking switch
0, 1
1
4
TBLK
UP_BLK: Top blanking
0~(7)~15
1
8
12
( ): Settings at center
5
BBLK
LO_BLK: Bottom blanking
0~(7)~15
0
13
13
6
VCMP V_COMP: Vertical compensation
0~15
0
0
0
7
HCMP H_COMP: Horizontal compensation
0~15
0
8
ACMP AFC_COMP: AFC compensation
0~7
0
9
PCMP PIN_COMP: Pin compensation
0~7
0
10
AFCM AFC_MODE: AFC loop gain
0~3
2
11
VFRQ
V_FREQ: Vertical frequency
0~3
12
VON
V_ON: Vertical drive on
0, 1
13
JUMP
JMP_SW: Reference pulse jump swtich
0, 1
0
14
VDJP
VDRV_SW: Vertical drive jump switch
0, 1
0
0
1
15
VDST
RST_SW: Vertical drive start switch
0, 1
0
0
1
16 EWDC EW_DC: Pin DC level shift
0, 1
0
17
AKBT
AKBTIM: AKB timing
0~31
20
20
10
Device Name: CXA2150AQ { CRT Driver / SONY } / IC201 (A-board) / P/N: 8-752-093-35 (SBorSD#: NA)
Slave Address: 86h
Slave Address: 86h
Note:
The same CXA2150 service data is used for DX1A-2001&2000.
The same CXA2150 service data is used for DX1A-2001&2000.
0
1
0
0
0
45
24
24
Full: 480p/960i (4x3) display
Vcomp1: 480p/960i (16x9) display
Vcomp2: 1080i (16x9) display
Vcomp1: 480p/960i (16x9) display
Vcomp2: 1080i (16x9) display
0
3
1
1
1
1
1
Data Initial/Average Settings
(32V&36V CRTs)
Register
No & Name
DX1A-2001&2000 SERVICE LIST (#4-3):
CXA2150D-3 {Deflection Controls: D3}
KV-32HS20/36HS20/36HS20H/32XBR450/36XBR450/36XBR450H
— 35 —
Control Register
Function & Link
Data
Type
Data
Range
Comment
480i
(15.75 KHz)
480p
(31.50 KHz)
1080i
(33.75 KHz)
0
MTRX MAT_OUT: Selection of color matrix conversion types
Micro
0~3
0
0
1
1
GAIN
GAIN_SEL:
Selection of output signals for SELYOUT, SELCBOUT, SELCROUT
Selection of output signals for SELYOUT, SELCBOUT, SELCROUT
C
0~3
0
2
CBGN
YGAIN, CBGAIN, CRGAIN:
The gain control of SELYOUT, SELCBOUT, & SELCROUT
The gain control of SELYOUT, SELCBOUT, & SELCROUT
C
0~15
9
3
VTC
V_TC: Setting of Vsync separation time constant
C
0~3
1
4
HWID
H_WIDTH: Setting of the output pulsewidth of SELHOUT
C
0~3
1
Video5Video6
Sub
5
HSEP
HSEP_SEL: Setting for the sync separation system
0, 1
0
0
0
6
TEST
TEST: Test mode selection (for device tests)
C
0, 1
0
7
FRGB
The forced RGB selection (for tests)
{0: MAT_OUT = MTRX (#0), 1: MAT_OUT = MTRX (#3)}
{0: MAT_OUT = MTRX (#0), 1: MAT_OUT = MTRX (#3)}
C
0, 1
0
Full
Vcomp1
Vcomp2
8
HMSK Hsync masking in vertical retrace
0, 1
0
Register
No & Name
Data Initial/Average Settings
(
32V&36V CRTs)
Device Name: CXA2151Q { Component I/F & Sync Seperation / SONY } / IC3001 (B-board) / P/N: 8-752-093-84 (SD#: S00302B)
Slave Address: 84h
Slave Address: 84h
DX1A-2001&2000 SERVICE LIST (#5):
CXA2151Q
Note:
The same CXA2151 service data is used for DX1A-2001&2000.
The same CXA2151 service data is used for DX1A-2001&2000.
1
Video5&6:
YPbPr-480i/480p/1080i inputs
Sub: 480i input from the sub-channel
YPbPr-480i/480p/1080i inputs
Sub: 480i input from the sub-channel
Full: 480p/960i (4x3) display
Vcomp1: 480p/960i (16x9) display
Vcomp2: 1080i (16x9) display
Vcomp1: 480p/960i (16x9) display
Vcomp2: 1080i (16x9) display
C: Common data
KV-32HS20/36HS20/36HS20H/32XBR450/36XBR450/36XBR450H
— 36 —
Control Register
Function & Link
Data
Type
Data
Range
Comment
Full
Vcomp1
Vcomp2
0
SBHS
DC AMP3: DC shift
Adj.
0~63
31 [31]
1
YBWU VCA9: Upper Y-bow
Adj.
0~63
31 [31]
2
YBWL VCA10: Lower Y-bow
Adj.
0~63
31 [31]
3
RSAP
DC AMP2: Right H-AMP
Adj.
0~63
31 [31]
4
RUBW VCA5: Right upper bow
Adj.
0~63
31 [31]
5
RLBW VCA6: Right lower bow
Adj.
0~63
31 [31]
6
LSAP
DC AMP1: Left H-AMP
Adj.
0~63
31 [31]
7
LUBW VCA1: Left upper bow
Adj.
0~63
31 [31]
8
LLBW VCA2: Left lower bow
Adj.
0~63
31 [31]
9
CADJ
DC AMP4: Offset adjustment (ADJ)
Adj.
0~63
10
CPY2
Copy Function 2: (Set CPY2=1, then press MUTE +
Enter.)
Enter.)
Micro
0, 1
For engineering design use only
Full: 480p/960i (4x3) display mode
Vcomp1: 480p/960i (16x9) display mode
Vcomp2: 1080i (16x9) display mode
Vcomp1: 480p/960i (16x9) display mode
Vcomp2: 1080i (16x9) display mode
Adj.: Adjusted data
From the system micro (V 2.0),
the deflection control-related initial settings
are the same as their average data.
the deflection control-related initial settings
are the same as their average data.
0
Note:
The same CXA8070 service data is used for DX1A-2001&2000.
The same CXA8070 service data is used for DX1A-2001&2000.
Data Initial Settings & [Average Data]
(
32V&36V CRTs)
Register
No & Name
48 [48]
31 [31]
31 [31]
31 [31]
31 [31]
31 [31]
31 [31]
31 [31]
31 [31]
31 [31]
31 [31]
31 [31]
31 [31]
31 [31]
31 [31]
31 [31]
DX1A-2001&2000 SERVICE LIST (#6):
D-CONV / CXA8070
Device Name: CXA8070AP { DY-Convergence Control / SONY } / IC5513 (D-board) / P/N: 8-759-595-52 (SB#: V1718)
Slave Address: DEh
Slave Address: DEh
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