DOWNLOAD Sony KP-HW512K90 Service Manual ↓ Size: 13.82 MB | Pages: 127 in PDF or view online for FREE

Model
KP-HW512K90
Pages
127
Size
13.82 MB
Type
PDF
Document
Service Manual
Brand
Device
TV
File
kp-hw512k90.pdf
Date

Sony KP-HW512K90 Service Manual ▷ View online

– 37 –
KP-HW512K90
RM-Y909K
BLOCK DIAGRAM (4)
3
6
7
10
9
10
9
11
12
13
BUFFER
Q341
BUFFER
Q332
2
BUFFER
Q333
1
27
26
25
20
20
16
31
2
3
13
BUFFER
Q334
35
34
33
1
5
12
43
42
41
22
23
4
5
+3.3V REG
IC8
39
30
29
6
5
4
2
10
9
8
7
35
54
43
6
7
28
27
30
9
21
21
6
2
3
18
8
9
12
25
6
2
1
7
BUFFER
Q373
20
21
22
13
12
28
42
MUTE
Q369
INV.BUFFER
Q378,379
LINIT
Q309,313,349,352
BUFFER
Q345
BUFFER
Q348
BUFFER
Q331,343
BUFFER
Q347,354
BUFFER
Q351,357
BUFFER
Q353
LIMITER
Q355,356
BUFFER
Q367
MUTE
Q342,346,350
R-R
R-G
R-B
R-YS
OSD-R
OSD-G
OSD-B
OSD-YS
VP
P MUTE
Q374
26
DAT1
CLK1
15
4
14
30
BUFFER
Q344
B
TO
B BOARD
CN3203
FOR CHECK
7
TO
A BOARD
SYSTEM
BLOCK
1
TO
A BOARD
SYSTEM
BLOCK
2
TO
A BOARD
I/V CONV
BLOCK
11
TO
A BOARD
SYSTEM
BLOCK
CN13
I
TO
CR BOARD
CN7102
H
TO
CG BOARD
CN7202
G
TO
CB BOARD
CN7302
L
TO
V BOARD
CN9001
K
TO
V BOARD
CN9001
J
TO
V BOARD
CN9001
CB
C22
CR
C21
SEL Y OUT
A19
SEL Y
SEL CB
SEL CR
VP
MID BUSY
SUB G
SUB YS
XSW
VD3
HD3
SWL2
SEL1
HD2
VD2
S-HD
S-VD
VD1
SEL CB OUT
C16
SEL CR OUT
A17
SUB G
C28
MID BUSY
C27
TH CONT
A30
SUB YS
A29
MID VD
A12
MID HD
A14
DRC SEL2
C14
DRC SEL1
C11
HD
A9
MID BINT
C29
MID BINT
SIG H
SIG V
SIRCS
VD
C9
S-HD
C24
S-VD
C25
VD1
C14
MID Y
A6
MID CR
A4
MID CB
C5
MID YS
C3
MID VS
C1
MID HS
A1
DAT1
C31
CLK
A32
RST
DAT1
CLK
RST
C18
VP
A32
Y
C20
CN5(1/2)
SCP
5
B
7
SIRCS
3
G
6
CN704
RS
1
IK
4
R
3
CN703
GS
1
IK
4
G
3
CN702
BS
1
OFFSET
5
B
3
CN19
M
4
CN18
VM
4
CN17
VM
4
IN3_3
S-Y
S-CB
S-CR
IN3_2
IN3_1
IN1_3
IN1_2
IN1_1
IN3_H
DAT1
CLK1
IN3_V
IN2_3
IN2_2
IN2_1
SELHOUT
SELVOUT
SELYOUT
SELYOUT
SELCROUT
EXTCLK/
XTAL
YG-IN
SDA
SCL
YG-OUT
D1-Y
D1-CB
D1-CR
D2-Y
D2-CB
D2-CR
X305
4MHz
X307
2.7MHz
IC306
COMPONENT-I/F
SEL Y
SEL CB
SEL CR
IC706
SHADING
IC705
SHADING
BUFFER
Q325
BUFFER
Q328
BUFFER
Q329
BUFFER
Q326
BUFFER
Q329
BUFFER
Q327
BUFFER
Q339
BUFFER
Q337
BUFFER
Q338
Y-M
Y-S
CB-M
CB-S
CR-M
CR-S
Y-M
Y-O
CB-O
CR-O
M/S
Y-S
CB-M
CB-S
CR-M
CR-S
XI
XO
DAT1
CLK1
VSIN
VDIN
SDA
SCL
IC305
YCT-SEL
IC308
ID-1 DECODER
SEL2
HP IN
VM LEVEL
V DRIVE+
V DRIVE–
V SHIFT
PROT MUTE
ABL
VP
ABL
H SAW
V COMP
PIN(E-W)
H DRIVE
SEL1
2
1
IC709(1/2)
SHADING AMP
21
24
7
G
R
B
X306
14.318MHz
Y
CB
CR
IC309
YC3
37
53
52
15
33
25
34
56
64
47
40
27
63
62
58
14
VCOMP
V_DRV+
V_DRV–
VM_MOD
HP_IN
HPROT
ABL_IN
EW_DRV
H_DRV
R2_IN
G2_IN
B2_IN
YSYM2
R1_IN
G1_IN
B1_IN
YSYM1
VPROT
VTIM
HC_PARA
CERA
DA
SCL
Y_IN
CB_IN
CR_IN
YF_OFF
DPDT_OFF
HS_IN
VS_IN
VBIAS
VREG5
SCP
R_OUT
G_OUT
B_OUT
IJ IN
VM_OUT
+5V
+3.3V
+6V
IC709(2/2)
IC710
SHADING AMP
D318
D321
A
(4/5) (VIDEO)
Q501
Q502
45
MP_PARA
IK
4
1
TO/FROM
BLOCK DIARAM(3)
– 38 –
KP-HW512K90
RM-Y909K
Y
CB
CR
Y-CL
CB-CL
CR-CL
100
102
117
7
8
9
10
11
156
157
161
160
162
95
96
97
-
-
-
-
20
13
32
25
49
46
42
35
DYO2
DYO9
DRO2
DRO9
DBO2
DBO9
V9O
HD2
C54O
DOM
XCAS
XRAS
XWE
XCS
DQ0
DQ15
ADDR0
ADDR11
DIY0
DIY7
DIC7
DIC0
CLP
ADHD
W13I
WPLLHD
IVD
C54I
RPLLHD
HREF
GAME
13
6
24
17
55
56
58
63
31
50
D(A)1
D(B)8
D(B)1
VIN(C)
VIN(A)
XSYNC
CLK
EXTCLP
VIN(B)
1
3
4
5
6
12
14
1
3
4
5
6
12
LOGIC VDD
VCO OUT
FINA
FINB
PFD OUT
VCO VDD
VCO IN
LOGIC VDD
VCO OUT
FINA
FINB
PFD OUT
VCO IN
14
+5V
-
-
-
-
2
12
39
49
19
24
27
32
DQ0
LDQM
WE
CAS 
RAS
CS
ADDR0
DQ15
UDOM
ADDR11
35
36
14
15
16
17
18
CLK
I
O
+2.5V
+3.3V
-
-
-
-
-
-
-
6
8
3
5
7
4
2
14
7
9
5
11
FL3003
100
2
3
1
99
96
98
C2
DRC-PXI
DRC-LINE-W
65
D0 95
C0 97
32
NVM-RST
CLK
DAT
AA
WP
RESET
33
NVM-WP
64
OSD-HSYNC
63
OSD-VSYNC
45
RST
DRC-INSEL
D2
TH CONT
DRC SEL2
C1
57 B-INT
D1
122
129
133
140
147
154
174
181
164
171
DRCDCLK
XDRCHS
XDRCVS
CB0-7
CR0-7
Y0-7
61 VSTILL0
59
69
PXI
Y0-7
C0-7
D(A)8
VDD
+3.3V REG.
Q3301
VCO LIMIT
Q3305
REG
Q3302
BUFFER
Q3307
BUFFER
Q3311
BUFFER
Q3309
LPF
(7.2MHz)
LPF
(3.6MHz)
LPF
(3.6MHz)
BUFFER
Q3306
BUFFER
Q3310
BUFFER
Q3308
BUFFER
Q3304
BUFFER
Q3303
BUFFER
Q3005
BUFFER
Q3006
BUFFER
Q3007
MIX
Q3408
MIX
Q3406
MIX
Q3405
BUFFER
Q3403
BUFFER
Q3407
BUFFER
Q3409
BIAS
SWITCH
Q3089,3090
B
HD
VP(V-FBP)
CB
Y
CR
CN3203(1/2)
C20
C22
A21
A9
VD
C9
SEL Y OUT
A19
SEL CB OUT C16
SEL CR OUT
TO
A BOARD
CN13
A17
DAT1
C31
CLK1
C37
TH CONT(X-SW) A30
DRC SEL2
C14
DRC SEL1
C11
MID BUSY
C27
SUB G
C28
SUB YS
A29
MID BINT
C29
A32
R-Y
B-Y
Y
R-Y
B-Y
Y
66 OSD-YS
69 G
S-HD
S-VD
53 SUB-BUSY
9
O_DRC_CD_SEL
10
55 VP-MAON
TH-Y
TH-CB
TH-CR
Y
CB
CR
Y-CL
CB-CL
CR-CL
LEVEL
SHIFT
Q3404
LEVEL
SHIFT
Q3402
B
(1/2) (DRC-MF)
IC3304
3-CH 8 BIT A/D CONVERTER
IC3303
DRC-MF
IC3305
WRITE PLL
IC3301
16M-SDRAM
IC3302
+1.8V REG
IC3306
READ PLL
IC3089
NVM
Q3091
IC3090
MID...COM
IC3091
RESET
2
TO/FROM
BLOCK DIARAM(6)
BLOCK DIAGRAM (5)
– 39 –
KP-HW512K90
RM-Y909K
BLOCK DIAGRAM (6)
X3402
X3402
74.175824MHz
17.2672MHz
42
44
46
2
14
5
11
7
9
I
O
I
O
+2.5V
+3.3V
+2.5V
13
20
3
10
23
30
51
44
71
62
61
52
R2
R9
G2
G9
B2
B9
RCK
BCK
RESET
GCK
RO
GO
BO
31
32
33
41
31
29
21
20
11
9
10
37
DSPY0
DSPY7
DSPCR0
DSPCR7
DSPCB0
DSPCB7
DRCYIN0
DRCYIN7
DRCCRIN0
DRCCRIN7
DRCCBIN0
DRCCBIN7
XDRCVS
XDRCHS
DRCDCLK
135
137
140
141
142
143
144
146
147
76
72
73
74
194
215
79
88
91
199
DSPCLK
DXT1OUT
DXT1IN
XRESET
SDDAT0
D0-D15
A0-A12
SDDAT31
SDADR12
SDCS
SDRAS
SDCAS
SDWE
SDCLKIN
SDCLK
SDCKE
SDDQM1
SDDQM0
DXT2IN
XDSPHS
XDSPVS
XDSPYS
VDOPLLHLD
VDOCLKIN
XVDOHS
196
202
IICSDA
ANYGIN
ANYCBIN
ANYCRIN
210
208
168 VDOYCLVL
169 VDOCBCLVL
170
93
IICSCL
94
VDOCRCLVL
17
18
19
20
67
68
28
59
16
71
13
74
85
31
42
22
27
60
66
DQ0
2
CKE
CLK
DQM2
DQM3
DQM0
DQM1
4
CY
DRC SEL2
TF CONT
CX
aY
aX
aO
CO
A
CO
5
13
12
bY
1
bX
PFD
INHIBIT
FIN B
FIN A
VCO OUT
VCO IN
PFD OUT
2
3
15
14
4
11
B 10
C 9
MID VDS
MID HD
MID Y
MID CB
MID CR
MID HS
MID VS
CN3203(2/2)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
BUFFER
Q3401
FL3401
1
16
8
11
3
14
5
2
7
12
9
6
157
148
167
158
119
99
120
134
Y0-7
CR0-7
CB0-7
HS
VS
DQ31
A0
A12
CS
CAS
RAS
WE
SDADR0
A6
A4
C5
A1
S-HD
C24
S-VD
C25
VD1
A15
C1
A14
MID YS
C3
A12
BUFFER
Q3410
BUFFER
Q3415
BUFFER
Q3414
BUFFER
Q3411
BUFFER
Q3413
BUFFER
Q3412
B
B
TO
A BOARD
CN13
R-Y
B-Y
Y
R-Y
B-Y
Y
9
3
12
6
1
2
4
+5V
+5V
+5V
+5V
5
201
XVDOVS
1
2
4
7
1
2
4
1
2
4
Y3I
Y OUT
TEX3I
V3I
VBX3I
U3I
UEX3I
V OUT
U OUT
CONT
CONT
CONT
(2/2) (DRC PROCESS,MULTI IMAGE DRIVER)
S-HD
S-VD
IC3410
D/A CONVERTOR
IC3403
IC3402
64M-SDRAM
IC3408
IMAGE DRIVER
IC3411(2/2)
IC3411(1/2)
IC3406
IC3404
WRITE PLL
IC3407
IC3405
IC3412
IC3403
+2.5V REG
IC3409
+2.5V REG
IC3413
SYNC SWITCH
IC3414
SELECTOR
2
TO/FROM
BLOCK DIARAM(5)
– 40 –
KP-HW512K90
RM-Y909K
BLOCK DIAGRAM (7)
18
7
26
27
28
49
47
50
48
44
9
12
36
32
33
34
11
6
46
60
61
62
59
55
8
39
17
16
15
4
IC1606
PJED-CPU
OR
OB
OG
O YS
I EXLC
38
OXLC
I EXODD
RESET
I OSC
O OSC
VBLK
DREG SCL
O DREG SDA
I DREG SDA
O I2C RST
O DREGI RST
O DREGI MUTE
O NAM
64
WRITE PROT O RAMCLR
O NVM STOP
MAIN SCL
SEN UI 
SEN LE
SEN R
SEN LO
MAIN SDA
I BINT
I VP
52
OVSHIFT
53
OHSHIFT
I HP
I DREG OVF
I DREG BSY
I DREG ACK
LEFT
UPPER
LOWER
RIGHT
S3001
SENSOR
CN3001
CN10
CN12
(X/X)
CN1601
HP
VP
1
1
7
6
5
7
6
5
1
2
3
1
2
3
7
6
5
7
6
5
1
2
3
1
2
3
3
5
7
SENSOR
LEFT
UPPER
LOWER
RIGHT
SCLCK
SDAT
X1601
12MHz
IC11
IC11
IC7
Q1603
IC5
IC10
IC10
(I/V CONV.)
A
(5/5)
S
(SENSOR)
S
(SENSOR)
S
(SENSOR)
S
(SENSOR)
RH
RV
GH
GV
BH
BV
8
7
5
4
2
1
C
TO G
BOARD
CN651
SEN U
4
SEN R
2
SEN LE
3
SEN LO
H SHIFT
V SHIFT
H CENT
DF
H SAW
REGI MUTE
HP
VP
RE YS
RE B
1
RH
RV
GH
GV
14
15
16
17
BH
BV
18
19
RE G
RE R
/BINT
CLK1
2
3
5
6
DAT1
PCLK
PDAT
RE B
RE G
RE R
BINT
SCLK
SDAT
PCLK
PDAT
7
9
10
4
2
3
1
6
7
8
10
11
13
14
15
20
1
6
7
8
10
11
13
14
15
20
1
14
15
16
17
18
19
2
3
5
6
7
9
10
SEN U
SEN R
SEN LE
SEN LO
H SHIFT
V SHIFT
H CENT
DF
H SAW
REGI MUTE
HP
VP
RE YS
RE B
RE G
RE R
BINT
SCLK
SDAT
PCLK
PDAT
SCLK
SDAT
PCLK
PDAT
RH
RV
GH
GV
BH
BV
V SHIFT
H CENT
D  FOCUS
H SAW
REGI MUTE
HP IN
VP
R-YS
R-B
R-G
R-R
PCLK
PDAT
/BINT
2
1
9
BINT
SCLK
SDAT
TO   A
BOARD
SYSTEM
BLOCK
9
TO   A
BOARD
VIDEO
BLOCK
3
TO   A
BOARD
VIDEO
BLOCK
2
FOR
CHECK
CN5 (2/2)
CN5 (2/2)
(1/2) (PJED-CPU)
AD
3
TO/FROM
BLOCK DIARAM(8)
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