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KLV-32V300A KLV-40V300A KLV-46V300A
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67
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7.32 MB
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Service Manual
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Device
TV
File
klv-32v300a-klv-40v300a-klv-46v300a.pdf
Date

Sony KLV-32V300A / KLV-40V300A / KLV-46V300A Service Manual ▷ View online

– 36 –
KLV-32/40/46V300A
RM-GA008
10. Set values of SREG_WB_GAM_R (B) 01_OFST as follows;
SREG_WB_R (B) 01_OFST
= SREG_WB_R (B) 02_OFST
+ [SREG_WB_R (B) 02_OFST-SREG_WB_R (B) 03_OFST]
11. Set values of SREG_WB_R06 ~ 07_OFST and
WB_B 06 ~ 07_OFST as follows;
SREG_WB_R (B) 07_OFST
= SREG_WB_R (B) 05_OFST
+ [SREG_WB_R (B) 05_OFST-SREG_WB_R (B) 04_OFST]
SREG_WB_R (B) 06_OFST
= SREG_WB_R (B) 05_OFST
+ [SREG_WB_R (B) 05_OFST-SREG_WB_R (B) 04_OFST] /2
12. Send ECS command: COLOR_SAVE
3-4-4.
White balance adjustment when color
temperature is “Warm 1”
1. Set up SREG_COLOR_TEMP = 2 (warm 1)
2. Set SREG_TEST_G_LEVEL = 204 (80 IRE)
3. Adjust values of SREG_WB_R (B) 05_OFST to be the chroma
in the below table
4. Set SREG_TEST_G_LEVEL = 128 (50 IRE)
5. Adjust values of SREG_WB_R (B) 04_OFST to be the chroma
in the below table
6. Set SREG_TEST_G_LEVEL = 76 (30 IRE)
7. Adjust values of SREG_WB_R (B) 03_OFST to be the chroma
in the below table
8. Set SREG_TEST_G_LEVEL = 51 (20 IRE)
9. Adjust values of SREG_WB_R (B) 02_OFST to be the chroma
in the below table
10. Set values of SREG_WB_GAM_R (B) 01_OFST as follows
SREG_WB_R (B) 01_OFST
= SREG_WB_R (B) 02 OFST
+ [SREG_WB_R (B) 02 OFST-SREG_WB_R (B) 03_OFST]
11. Set values of SREG_WB_R06 ~ 07_OFST and WB_B06 ~
07_OFST as follows;
SREG_WB_R (B) 07_OFST
= SREG_WB_R (B) 05_OFST
+ [SREG_WB_R (B) 05_OFST-SREG_WB_R (B) 04_OFST]
SREG_WB_R (B) 06_OFST
= SREG_WB_R (B) 05_OFST
+ [SREG_WB_R (B) 05_OFST-SREG_WB_R (B) 04_OFST] /2
12. Send ECS command: COLOR_SAVE
Internal
signal
(IRE)
SREG
_Test_G
_LEVEL
SPEC
target
46"
40"
32"
20
51
0.5->0.7->1JND
.0014->.00196->.0028
0.5->0.7->1JND
.0014->.00196->.0028
0.5->0.7JND
0.0014->0.00196
0.3->0.5JND
0.0008->0.0014
0.2869
0.2890
<-
0.2975
0.2943
0.1914
0.1942
0.4465
0.4449
0.2880
0.2887
0.2981
0.2917
0.1920
0.1950
0.4471
0.4432
0.2885
0.2895
0.2991
0.2996
0.1919
0.1925
0.4477
0.4482
0.2895
0.2934
0.2997
0.3018
0.1924
0.1945
0.4483
0.4501
0.2880
0.2911
0.1947
0.4428
0.2871
0.2903
0.1943
0.4421
0.2887
0.2976
0.1927
0.4469
0.2922
0.3003
0.1942
0.4490
30
76
50
128
80
204
x
y
u'
v'
x
y
u'
v'
x
y
u'
v'
x
y
u'
v'
The target of White balance adjustment when color temperature is “Warm1”.
3-4-5.
White balance adjustment when color
temperature is “Warm 2”
1. Set up SREG_COLOR_TEMP = 3 (Warm 2)
2. Set SREG_TEST_G_LEVEL = 204 (80 IRE)
3. Adjust values of SREG_WB_R (B) 05_OFST to be the chroma
in below table
4. Set SREG_TEST_G_LEVEL = 128 (50 IRE)
5. Adjust values of SREG_WB_R (B) 04_OFST to be the chroma
in below table
6. Set SREG_TEST_G_LEVEL = 76 (30 IRE)
7. Adjust values of SREG_WB_R (B) 03_OFST to be the chroma
in below table
8. Set SREG_TEST_G_LEVEL = 51 (20 IRE)
9. Adjust values of SREG_WB_R (B) 02_OFST to be the chroma
in below table.
10. Set values of SREG_WB_GAM_R (B) 01_OFST as follows;
SREG_WB_R (B) 01_OFST
= SREG_WB_R (B) 02_OFST
+ [SREG_WB_R (B) 02_OFST-SREG_WB_R (B) 03_OFST]
11. Set values of SREG_WB_R06 ~ 07_OFST and
WB_B06 ~ 07_OFST as follows
SREG_WB_R (B) 07_OFST
= SREG_WB_R (B) 05_OFST
+ [SREG_WB_R (B) 05_OFST-SREG_WB_R (B) 04_OFST]
SREG_WB_R (B) 06_OFST
= SREG_WB_R (B) 05_OFST
+ [SREG_WB_R (B) 05_OFST-SREG_WB_R (B) 04_OFST] /2
12. Send ECS command: COLOR_SAVE
3-5.
Panel Replacement
When replacing the panel please reset the gamma and white balance
before performing W/B for new panel.
3-6.
Board Replacement
3-6-1.
BG1 Board Replacement
When replacing the BG1 board please readjust the AD and readjust
the W/B.
Internal
signal
(IRE)
SREG
_Test_G
_LEVEL
SPEC
target
46"
40"
32"
20
51
0.5->0.7->1JND
.0014->.00196->.0028
0.5->0.7->1JND
.0014->.00196->.0028
0.5->0.7JND
0.0014->0.00196
0.3->0.5JND
0.0008->0.0014
0.3191
0.3133
0.3261
0.3130
0.2034
0.2045
0.4677
0.4596
0.3238
0.3157
0.3245
0.3090
0.2074
0.2078
0.4675
0.4577
0.3326
0.3261
0.3403
0.3283
0.2073
0.2075
0.4772
0.4699
0.3136
0.3185
0.3255
0.3182
0.1998
0.2061
0.4666
0.4633
0.3119
0.3097
0.2048
0.4575
0.3135
0.3069
0.2071
0.4561
0.3248
0.3271
0.2070
0.4691
0.3166
0.3161
0.2056
0.4618
30
76
50
128
80
204
x
y
u'
v'
x
y
u'
v'
x
y
u'
v'
x
y
u'
v'
The target of White balance adjustment when color temperature is “Warm2”.
– 37 –
KLV-32/40/46V300A
RM-GA008
SECTION 4
DIAGRAMS
4-1.
BLOCK DIAGRAM
4-1-1.
H1, H3, H4 AND UT BLOCK DIAGRAMS
10
9
8
4
7
5
6
3
STBY3.3V
SIRCS
VD3.3V
BL_IN
STBY_LED
PICTURE_OFF_LED
ON_TIMER_LED
PWR/RESERVE_LED
REC/RESERVE_LED
2
2
3
6
5
7
4
8
9
10
3
2
KEY1
POWER_INT
19
20
Q303,304
LED
SW
SW
LED
Q301,302
D305
POWER
PIC OFF
D302
Q305
LED SW
D308
STANDBY
ILLUM
SENSOR
IC320
STBY3.3V
H3
(LED)
Q320
CN101
POWER
S101
KEY
S102-S107
H1
(KEY)
H4 (OPTICAL
SENSOR)
CN351
CN401
SIRCS
IC401
TO
BG1 BOARD
CN3008
IC8001
UT
(USB HOST MICRO)
3
2
1
8
7
50
23
12
11
22
CN8002
PANEL UNIT
TO
Q8004,8005
IC8000
Q8000
Q8003
20
Q8002
IC8002
+D3.3V
+D5V
15
11
12
14
8
10
7
5
6
2
15
56
57
14
26
58
25
29
62
64
LOG_RXD
SR_CLK
SIR_OUT
SIR_IN
LOG_TXD
HOST_ST1
HOST_ST0
RPLY_USB
INT_USB_HOST
RST_MICRO
CN8001
2,17
3,16
6
4
CN8003
TXD
RXD
MD0
RES
TO
BG1 BOARD
CN3004
TO BG1 BOARD
CN3500
– 38 –
KLV-32/40/46V300A
RM-GA008
4-1-2.
U1 BLOCK DIAGRAM
HP_DET
HP_OUT_AU_R
HP_OUT_AU_L
V2_IN_S2SW
V2_IN_SSW
V2_IN_AU_R
V2_IN_AU_L
V2_IN_C
V2_IN_Y
V2_IN_V
CN201
18
14
8
1
5
6
10
9
13
15
2
1
4
3
U1
(SIDE INPUT) 
J201
J202
S VIDEO
VIDEO
VIDEO IN
2
AUDIO
R
L
TO BG1 BOARD
CN1400
– 39 –
KLV-32/40/46V300A
RM-GA008
4-2.
CIRCUIT BOARDS LOCATION
G
D
S
B1 E1
C2
B2 C1
E2
G
D
S
B2 E2
C1
B1 C2
E1
B2 E2
C1
B1 C2
E1
B2 E2
C1
B1 C2
E1
B1 E1
E2
C1(B2)
C2
B1
E2
C1
C2
(B2)
E1
(B2)
E1
E2
B1
C2
C1
B1
E1
C2
B2
C1
E2
G
S
S
D
G
D
B1
E1
C2
B2
C1
E2
B1
E2
C2
C1(B2)
E2
B1
C1
C2
E1(B2)
C2
B1
C1
E2
E1(B2)
C2
B1
C1
E2
B2
E1
C2
Transistor
(FET)
Transistor
Transistor
Transistor
Transistor
Transistor
Transistor
Transistor
Transistor
Transistor
Diode
Diode
Diode
Diode
Diode
Diode
Diode
Diode
Diode
Diode
Source
Source
Anode
Anode
(NC)
(NC)
Cathode
Anode
Cathode
Common
Cathode
Cathode
Common
Cathode
Cathode
Common
Common
Common
Common
Cathode
Anode
Base
Emitter
Collector
Base
Emitter
Collector
Drain
Gate
Gate
Drain
Device
Printed symbol
Terminal name
Circuit
Anode
Anode
Anode
Cathode
Anode
Anode
Cathode
Transistor
(FET)
Transistor
(FET)
Emitter
Collector
Base
Transistor
Source
Gate
Drain
Cathode
Anode
Anode
Cathode
Anode
Anode
4-3.
SCHEMATIC DIAGRAM INFORMATION
Note:
All capacitors are in µF unless otherwise noted.(pF:µµF)
Capacitors without voltage indication are all 50V.
Indication of resistance, which does not have one for rating
electrical power, is as follows.
Pitch: 5 mm
Rating electrical power 1/4W (CHIP: 1/10W)
All resistors are in ohms.
: nonflammable resistor.
: fusible resistor
¢
: internal component.
: panel designation or adjustment for repair.
All variable and adjustable resistors have characteristic curve B
unless otherwise noted.
All voltages are in V.
: earth-ground
: earth-chassis
All voltages are in V.
Readings are taken with a 10 M digital multimeter.
Readings are taken with a color-bar signal input.
Voltage variations may be noted due to normal
production tolerances.
: Cannot be measured.
NO MARK : PAL
Circled numbers are waveform references.
:  B  +bus.
:  B  –bus.
 
 
k
: signal path.
Reference information
RESISTOR
: RN
METAL FILM
: RC
SOLID
: FPRD
NONFLAMMABLE CARBON
: FUSE
NONFLAMMABLE FUSIBLE
: RW
NONFLAMMABLE WIREWOUND
: RS
NONFLAMMABLE METAL OXIDE
: RB
NONFLAMMABLE CEMENT
COIL
: LF-8L
MICRO INDUCTOR
CAPACITOR
: TA
TANTALUM
: PS
STYROL
: PP
POLYPROPYLENE
: PT
MYLAR
: MPS
METALIZED POLYESTER
: MPP
METALIZED POLYPROPYLENE
: ALB
BIPOLAR
: ALT
HIGH TEMPERATURE
: ALR
HIGH RIPPLE
Note:
The component identified by shading and
mark 
! are critical for safety. Replace only with
part number specified.
Note: The components identified by mark   contain
confidential information. Strictly follow the instructions
whenever the components are repaired and /or replaced.
H1 Board
U1 Board
BG1 Board
H3 Board
G1V Board
UT Board
H4 Board
H1 Board
U1 Board
BG1 Board
D2 Board (KLV-46V300A)
H3 Board
G3 Board
D1 Board
UT Board
H4 Board
KLV-40/46V300A
KLV-32V300A
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