Sony KDL-20G3000 / KDL-20G3030 Service Manual ▷ View online
- 24 -
~ B2 Board Schematic Diagram [ Main Microcontroller, Scarts, AV Side & Component Input ] Page 2C/13 ~
11
22
Q
O
P
A
B
C
D
E
F
G
H
J
I
K
L
M
N
12
13
14
15
16
17
18
19
20
21
*R7201
XX
XX
*R7216
TP7207
470
*R7206
JL7207
TP7220
JL7202
JL7205
1k
*RB7204
2
1
4
3
6
5
8
7
470
*R7207
GND_1
XX
*R7210
JL7209
XX
*R7214
1k
*R7204
*
GND_1
XX
*R7211
4.7k
*R7208
XX
*R7215
JL7203
1
*R7
TP7218
*R7202
1k
TP7208
FE_FTV_CONFIG0
JL7210
TP7219
FE_FTV_CONFIG2
JL7208
GND_1
JL7204
XX
*R7209
JL7211
JL7206
XX
*R7
FE_FTV_CONFIG1
FE_RADD[19-25]
XX
*R7212
GND_1
0
*C7
XX
*R7213
GND_1
1k
RB7202
2
1
4
3
6
5
8
7
10
9
12
11
14
13
16
15
1k RB7200
2
1
4
3
6
5
8
7
10
9
12
11
14
13
16
15
FE_CI_TSD[0-7]
FE_RADD[23]
FE_RADD[21]
FE_RADD[24]
FE_RADD[19]
FE_RADD[22]
GND_1
FE_RADD[25]
FE_RADD[20]
3.3V_MAIN
GND_1
FE_RDATA[0]
FE_RDATA[4]
FE_RDATA[5]
FE_RDATA[3]
FE_CI_TSD[3]
FE_RDATA[6]
FE_CI_TSD[7]
FE_RDATA[1]
FE_CI_TSD[5]
FE_CI_TSD[6]
FE_RDATA[2]
FE_CI_TSD[1]
FE_CI_TSD[4]
FE_RDATA[7]
FE_CI_TSD[0]
FE_CI_TSD[2]
PLACE R7201 &
R7202 ADJACENT
R7202 ADJACENT
BOARD VERSION RESISTORS - MOUNT ON
SIDE-A
SIDE-A
PLEASE PLACE COMPONENTS IN
EJTAG_MODE
DINT_EN
TO FORCE "BOOT FROM MEMORY STICK",
CONNECT (SHORT) TP7207 TO TP7208, OR
CONNECT (SHORT) JL7200 TO JL7201
CONNECT (SHORT) TP7207 TO TP7208, OR
CONNECT (SHORT) JL7200 TO JL7201
BOARD VERSION RESISTORS - MOUNT ON
SIDE-B WITH JL’S ON SIDE-B
SIDE-B WITH JL’S ON SIDE-B
NANDCS
PCIMODE
27M
RDATA[0] = 1 = ENDIAN = Big Endian
RDATA[2:1] = 10 = MRGMODE1-0 = Full merge & All bytes
RDATA[3] = -- = RESERVED
RDATA[5:4] = 10 = VRCLKSEL1-0 = 187MHz
RDATA[8:6] = 101 = MCLKSEL2-0 = 166MHz
RDATA[9] = 1 = ROMBEND = Big Endian
RDATA[10] = 1 = BWSEL = 8bit
RDATA[11] = 1 = MINIBOOT = use miniboot
RDATA[13:12] = 11 = BOOTSEL1-0 = Nand, then Memory Stick
RDATA[15:14] = 00 = BOOT_NAND_SEL1-0 = <256mbit
RADD[25] = 1 = EJTAG_MODE = EJTAG
RADD[24] = 0 = DINT_EN = disable
RADD[23] = 1 = DSYSELB = main only
RADD[22] = 1 = PCIMODE = host
RADD[21:20] = 00 = PCI_SIZE1-0 = 32Mbyte
RADD[19] = 0 = NANDCS = CS0
RDATA[2:1] = 10 = MRGMODE1-0 = Full merge & All bytes
RDATA[3] = -- = RESERVED
RDATA[5:4] = 10 = VRCLKSEL1-0 = 187MHz
RDATA[8:6] = 101 = MCLKSEL2-0 = 166MHz
RDATA[9] = 1 = ROMBEND = Big Endian
RDATA[10] = 1 = BWSEL = 8bit
RDATA[11] = 1 = MINIBOOT = use miniboot
RDATA[13:12] = 11 = BOOTSEL1-0 = Nand, then Memory Stick
RDATA[15:14] = 00 = BOOT_NAND_SEL1-0 = <256mbit
RADD[25] = 1 = EJTAG_MODE = EJTAG
RADD[24] = 0 = DINT_EN = disable
RADD[23] = 1 = DSYSELB = main only
RADD[22] = 1 = PCIMODE = host
RADD[21:20] = 00 = PCI_SIZE1-0 = 32Mbyte
RADD[19] = 0 = NANDCS = CS0
DSYSELB
STRAP PINS
THIS BOX IN SAME AREA ON PWB
S/W O
PCI_SIZE1
PCI_SIZE0
ROMBEND
ENDIAN
VRCLKSEL0
BOOT_NAND_SEL_0
MCLKSEL0
MRGMODE1
MCLKSEL1
RESERVED
BWSEL
VRCLKSEL1
MINIBOOT
MCLKSEL2
BOOTSEL0
MRGMODE0
BOOTSEL1
BOOT_NAND_SEL_1
3.3V_MAIN
3.3V_MAIN
3.3V_MAIN
3.3V_MAIN
3.3V_MAIN
COMPONENTS MARKED AS XX REFER TO PARTS LIST, WILL ONLY BE LISTED IF FITTED
B2
2C/13
- 25 -
~ B2 Board Schematic Diagram [ Main Microcontroller, Scarts, AV Side & Component Input ] Page 2D/13 ~
11
21
22
R
Q
P
EE
FF
S
T
U
V
W
X
Y
Z
AA
BB
CC
DD
20
18
19
17
15
16
14
12
13
10k
*R7226
RESET_N
JL7207
GND_1
TP7220
JL7205
TP7221
RT1N141M-TP-1
Q7203
1005
1/16W
CHIP
5%
R7243
10k
JL7209
0 . 1
*C7212
S
2SK2036(TE85L)
Q7201
XX
*R7225
0uH
*FB7201
GND_1
*X7200
0.1
*C7208
*R7224
10k
10k
*R7221
TP7218
SCL
0 . 1
*C7210
GND_1
FE_CLK27M
1005
1/16W
CHIP
5%
R7242
10k
SCL_EMMA
0
XX
*R7222
JL7210
SDA_EMMA
100
*R7219
TP7219
0 . 0 0 1
*C7205
2
JL7208
GND_1
JL7204
TP7222
FE_PWMOUT
XX
*C7207
JL7211
8
7
6
5
4
3
2
1
*IC7202
X1
NC
VIN
GND
CLK
VDD
PD
X2
JL7206
XX
*R7220
1
GND_1
SDA
RT1P431M-TP-1
Q7204
*
47
*R7233
10k
*R7223
0 . 1
*C7204
XX
*C7206
1k
*R7227
4.7
*C7211
4 . 7
*C7209
XX
R7236
R7239
XX
R7240
XX
XX
R7245
S
2SK2036(TE85L)
Q7202
XX
*C7237
GND_1
GND_1
GND_1
GND_1
3.3V_MAIN
GND_1
RS - MOUNT ON
0
FTV_CONFIG2
DDR SDRAM
LAYOUT NOTE:-
REMOVE GND PLANE AROUND AND UNDERNEATH IC7202
AND X7200 INCLUDING TRACKS FROM XTAL TO IC.
REMOVE GND PLANE AROUND AND UNDERNEATH IC7202
AND X7200 INCLUDING TRACKS FROM XTAL TO IC.
0.5%
FTV_CONFIG0
0
0
OPTION #2
FTV_CONFIG1
RS - MOUNT ON
DE-B
PLACE THESE CLOSE TO PIN 49 OF IC
27MHZ CLOCK
0
OPTION #3
OPTION #1
0
0
0
0
S/W OPTION SELECT RESISTORS
0
3.3V_MAIN
3.3V_MAIN
3.3V_MAIN
B2
2D/13
- 26 -
~ B2 Board Schematic Diagram [ Main Microcontroller, Scarts, AV Side & Component Input ] Page 3A/13 ~
O
P
10
A
B
C
D
E
F
G
H
J
I
K
L
M
N
1
2
3
4
5
6
7
8
9
11
12
Q
3.3V_MAIN
*R7304
10k
*R7302
10k
XX
*R7307
FE_IOWRB
*C7303
1000p
14
13
12
11
10
9
8
7
1
2
3
4
5
6
*IC7303
1A
1Y
2A
2Y
3A
3Y
GND
4
Y
4A
5Y
5A
6Y
6A
VCC
*C7306
0 . 1
*R7308
100
*R7313
47
*C7304
0 . 1
FE_CI1_INPACKB
*C7312
XX
20
19
18
17
16
15
14
13
12
11
12345678
91
0
*IC7305
OE1
A0
A1
A2
A3
A4
A5
A6
A7
GND
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
OE2
VCC
FE_CI1_CE1B
20
19
18
17
16
15
14
13
12
11
12345678
91
0
*IC7306
OE1
A0
A1
A2
A3
A4
A5
A6
A7
GND
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
OE2
VCC
*R7312
47
*C7307
0 . 1
FE_CI1_WAITB
FE_FWEB
FE_RADD[0-11]
*FB7301
0uH
*R7303
10k
*C7305
1000p
FE_IOWRB_FWEB
FE_CI1_IREQB
*FB7303
0uH
*C7302
0 . 1
*R7315
47
*C7308
0 . 1
*FB7304
0uH
GND_1
FE_CI1_RSTB
*FB7305
0uH
FE_NCI_EN
*R7306
220
FE_FOEB
FE_M_CKOUT,FE_M_SYNC,FE_M_VAL
*R7305
100
FE_BUF_DIR
FE_IORDB
*R7309
10k
*R7316
47
20
19
18
17
16
15
14
13
12
11
12345678
91
0
*IC7304
OE1
A0
A1
A2
A3
A4
A5
A6
A7
GND
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
OE2
VCC
*FB7302
0uH
FE_REGB
*R7314
47
FE_M_DATA[0-7]
54
3
2
1
*IC7302
A
B
GND
Y
VCC
FE_CI_TSD[7]
FE_FOEB
FE_CAM_TSISYNC
FE_RADD[8]
FE_CAM_ADD[10]
FE_CAM_TSOD[5]
FE_D_IOWRB
F
FE_CI1_WAITB
FE_RADD[9]
FE_IORDB
FE_
FE_
FE_RADD[11]
FE_IORDB
FE_CAM_TSOD[7]
FE_CI1_RSTB
FE_CI_TSD[5]
FE_CI1_CE1B
F
FE_CAM_TSOD[3]
FE_CAM_ADD[11]
FE_CAM_ADD[8]
FE_CAM_TSID[2]
FE_FWEB
FE_CAM_TSOD[4]
FE_CAM_TSID[3]
FE_CI_TSD[4]
FE_CI1_IREQB
FE_FWEB
FE_CI1_RSTB
FE_CI1_CE1B
FE_D_IOWRB
FE_CI_TSD[6]
FE_CAM_ADD[9]
FE_CI_TSD[3]
FE_M_DATA[3]
FE_REGB
FE_
FE_M_DATA[2]
FE_CAM_TSID[1]
FE_CI1_INPACKB
FE_M_SYNC
FE_M_DATA[1]
FE_CAM1_IREQB
FE_M_DATA[0]
FE_RADD[10]
FE_CAM_TSID[0]
FE
FE_FOEB
FE_CAM_TSOD[6]
F
EMMA2LR
EMMA2LR
EMMA2LR
EMMA2LR
TS to CAM
POWER
B2.-SE2
B2
3A/13
3.3V_MAIN
3.3V_MAIN
3.3V_MAIN
- 27 -
~ B2 Board Schematic Diagram [ Main Microcontroller, Scarts, AV Side & Component Input ] Page 3B/13 ~
DD
CC
BB
P
EE
FF
Z
1
2
3
4
5
6
7
8
9
10
11
12
Q
R
S
T
U
V
W
X
Y
AA
*R7322
100
*R7321
100
FE_CI1_CD2B
A1
B1
A2
B2
A3
B3
A4
A5
A6
B4
B5
B6
A7
B7
A8
B8
A9
B9
A10
B10
A11
B11
A12
B12
A13
B13
A14
B14
A15
B15
A16
B16
A17
B17
A18
B18
A19
B19
A20
B20
A21
B21
A22
B23
A23
B22
179376921
GND
D3
D4
D5
D6
D7
CE1#
A10
OE#
A11
A9
A8
A13
A14
WE#
IREQ#
VCC
VPP1
MIVAL
MCLKI
A12
GND
CD1#
MDO3
MDO4
MDO5
MDO6
MDO7
CE2#
VS1#
IORD#
IOWR#
MISTRT
MDI0
MDI1
MDI2
MDI3
VCC
VPP2
MDI4
MDI5
MDI6
A7
MDI7
A6
MCLKO
FE_CI1_VS1B
*R7323
10k
*R7313
47
*C7312
XX
*R7312
47
*R7320
100
*R7328
10k
*R7325
10k
*R7324
10k
*R7332 1k
*R7315
47
FE_CI1_CD1B
*R7316
47
*R7314
47
*R7333 47
FE_CI_TSD[7]
FE_CAM_TSIVAL
FE_CAM_TSISYNC
FE_CAM_TSOD[3]
FE_CAM_ADD[10]
FE_CAM_DAT[4]
FE_CAM_OEB
FE_CAM_OEB
FE_CAM_ADD[8]
FE_CAM1_CE1B
FE_CAM_TSID[3]
FE_CAM_ADD[10]
FE_CAM1_RSTB
FE_CAM_TSID[0]
FE_CAM_IORDB
FE_CAM_DAT[7]
FE_CAM_TSID[6]
FE_CI_TSD[5]
FE_CAM1_IREQB
FE_CAM_WEB
FE_CAM_ADD[9]
FE_CAM_ADD[7]
FE_CAM_TSID[5]
FE_CAM_TSOD[4]
FE_CAM_ADD[11]
FE_CAM_ADD[8]
FE_CAM_TSID[1]
FE_CAM_TSID[2]
FE_CAM_TSID[3]
FE_CI_TSD[4]
FE_CAM_TSOD[5]
FE_CAM_DAT[5]
FE_CAM_DAT[3]
FE_CI_TSD[6]
FE_CAM_TSID[2]
FE_CAM_TSISYNC
FE_CAM_TSOCLK
FE_CAM_TSID[4]
FE_CAM_DAT[6]
FE_CAM_TSICLK
FE_CAM_ADD[9]
FE_CAM_ADD[6]
FE_CAM_IOWRB
FE_CI_TSD[3]
FE_CAM_ADD[11]
FE_CAM_IOWRB
FE_CAM_TSID[1]
FE_CAM_TSID[7]
FE_CAM_TSOD[7]
FE_CAM_TSOD[6]
FE_CAM_TSID[0]
FE_CAM1_CE1B
FE_CAM_WEB
FE_CI1_IREQB
FE_CAM_IORDB
TS to CAM
TS from CAM
PCMCIA DVB-CI CONNECTOR
EMMA2LR
B2
3B/13
AIN
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