Sony KDE-V42A12U / KE-V42A10E Service Manual ▷ View online
* Notice :
1) Check whether there are foreign materials or not on the connector before assembling of TCP.
2) Be careful not to take a damage on the board by ESD during handling of TCP.
3)
The misassembling of TCP is the cause of defect.
5.2.4 Exchange of Logic Buffer Board
1) Disassemble the chassis cover on TCP and disconnect FFC Cable.
2) Disjoint Logic Buffer Board.
3) Assemble New Board and connect FFC Cable.
4) Finally joint the chassis cover.
5.2.5 Exchange Y-Buffer Board and Y-Main board
1) Disconnect all of the FPC connector of Y-Buffer Board. (Upper and Lower)
2) Separate all of the connector of Y-Main.
3) Remove the Y Main board and Y Buffer Board without separating both board.
4) Disconnect CN5003, CN5004 and then disconnect CN5005, 5006, 5007, 5008 to separate
both board.
5) Replace the defected board.
6) Connect the connector of CN5005, 5006, 5007, 5008 and then connect CN5003, CN5004
to reassemble Y Buffer Board and Y-Main.
7) Arrange the board on the chassis and then screw to fix.
8) Connect the FPC.
9) Supply the electric power to the module and then check the waveform of board.
10) Turn off the power after the waveform is adjusted.
5.2.6 Exchange X-Main board
1) Pull out the FFC Cable. [Refer to Photo 3]
2) Remove the board from chassis.
3) Assemble New Board and connect FFC Cable.
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6. Operation Check after Repair Service
6.1 Check Item
Check Item
Specification
Remarks
Module
assemble
check
TCP Assembling
condition
Securely connected or
tightened
Drive board
Y BUFFER
Logic & Logic
Buffer
Harness
Securely connected
Material Mixing
No material mixing
.
6-2 Check Procedure
1) Visual check as following
a. Assembling condition of module.
b. No problem on the connection of module.
c. The grounding and easily short-circuited parts are not damaged.
2) Turn on the power to PDP module, and then check that LED lights up and the SET is working
well.
3) Check the power voltage after turn on the power.
4) Check whether something wrong.
5) If something wrong, check and adjust the waveform by using Oscilloscope according to the
adjustment specification.
6) Check the panel condition by adjusting the Pattern Generator Level.
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7. Operation Check
7.1 Adjustment Specification, Checking Position etc.
■ V4 TCP Ramp Waveform Inclination Adjustment ( Y-Board )
[ Rising Ramp ] [ Falling Ramp ]
Adjust VR5001 to set the time of
Yrr( Rising Ramp) 60㎲±2㎲
Adjust VR5003 to set the time of
Yfr (Falling Ramp_2st) 80㎲±2㎲
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7.2 Adjusting procedure
1) Get Pattern to be Full White.
2) Check the waveform using Oscilloscope
① Triggering through V_TOGG of LOGIC Board.
② Connect the OUT240 Test Point(U5404) at the center of Y_buffer to other channel, and then check the
2nd SF operating waveform of 1TV-Field.
③ Check the waveform as before by adjusting Horizontal Division.
Check the Reset waveform when the V_TOGG Level is changed.
④ Set the Vset to
60us
by adjusting
VR5001.
⑤ Set the Falling maintenance time to
80us
by adjusting R5003.
▶ VR5001 Adjustment
- Rising Ramp flat time Typ. 60㎲±2㎲
▶ VR5003 Adjustment
- Falling Ramp flat time Typ. 80㎲±2㎲
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