DOWNLOAD Sony RM-PJ2 / VPL-DS100 Service Manual ↓ Size: 4.23 MB | Pages: 75 in PDF or view online for FREE

Model
RM-PJ2 VPL-DS100
Pages
75
Size
4.23 MB
Type
PDF
Document
Service Manual
Brand
Device
Projector
File
rm-pj2-vpl-ds100.pdf
Date
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2-9
VPL-DS100
2.
In the LOW mode of W/B, adjust the GAIN R for 
+15
higher than the value in the HIGH mode, adjust the
GAIN G for 
_25 lower than the value in the HIGH
mode and adjust GAIN B that is the same as the value
in the HIGH mode.
3.
Measure the chromaticity (x, y).
4.
Input the 30 IRE flat field signal.
5.
Adjust the BIAS R and BIAS B in the LOW mode of
W/B until the chromaticity (x, y) that is measured at
step 3 is obtained.
6.
Input the 80 IRE flat field signal.
7.
Adjust the GAIN R and GAIN B in the LOW mode of
W/B until the chromaticity (x, y) that is measured at
step 3 is obtained.
8.
Repeat steps 4 to 7 until the chromaticity (x 
±
0.002, y
±
0.004) with reference to the chromaticity (x, y) that
is measured at step 3 is obtained.
9.
Press the MEMORY key and save the adjustment
value.
2-5-3. HIGH Mode of VIDEO
1.
Input the NTSC or PAL video signal to the input
connector.
2.
In the HIGH mode of W/B, adjust the GAIN R for
_20 lower than the value in the INPUT-A HIGH
mode, adjust the GAIN G for 
_35 lower than the value
in the INPUT-A HIGH mode and adjust GAIN B that
is the 
_20 lower than the value in the INPUT-A HIGH
mode.
3.
Adjust BIAS G for 
_5 lower than the value in the
INPUT-A HIGH mode, adjust the BIAS R and BIAS
B for the same value as those of the INPUT-A HIGH
mode.
4.
Press the MEMORY key and save the adjustment
value.
2-5-4. LOW Mode of VIDEO
1.
Input the NTSC or PAL video signal to the input
connector.
2.
In the LOW mode of W/B, adjust the GAIN R for 
_20
lower than the value in the INPUT-A LOW mode,
adjust the GAIN G for 
_35 lower than the value in the
INPUT-A LOW mode and adjust GAIN B that is the
_20 lower than the value in the INPUT-A LOW mode.
3.
Adjust BIAS G for 
_5 lower than the value in the
INPUT-A LOW mode, adjust the BIAS R and BIAS B
for the same value as those of the INPUT-A HIGH
mode.
4.
Press the MEMORY key and save the adjustment
value.
2-5. White Balance Adjustment
Preparation before adjustment
1.
Input the 100 IRE flat field signal to the INPUT-A
connector and allow the warm-up of 10 minutes aging
at a minimum.
2.
Enter the Service Mode.
Press the keys in the following order.
[ENTER] 
→
 [ENTER] 
→ 
 [(] 
 →
 
 
[)] 
 → 
[ENTER].
The message [Do you want to enter the Service Mode?
Yes : 
↑ 
 No : 
↓
] appears.
Select [Yes : 
↑
].
[Supplementary information: How to Exit the
Service Mode]
Perform the step 2 KEY operation.
The message [Do you want to return to the User Mode?]
appears.
Select [Yes : 
↑
].
2-5-1. HIGH Mode of INPUT-A
Connect the10-step signal to the INPUT-A connector and
measure the chromaticities at each brightness.
If chromaticities are different at each brightness, perform
the following adjustment.
1.
Input the 100 IRE flat field signal to the INPUT-A
connector.
2.
Measure the chromaticity (x, y).
3.
Input the 80 IRE flat field signal.
4.
Adjust the GAIN R and GAIN B in the HIGH mode of
W/B until the chromaticity (x, y) that is measured at
step 2 is obtained.
5.
Input the 30 IRE flat field signal.
6.
Adjust the BIAS R and BIAS B in the HIGH mode of
W/B until the chromaticity (x, y) that is measured at
step 2 is obtained.
7.
Repeat steps 3 to 6 until the chromaticity (x 
±
0.002, y
±
0.004) with reference to the chromaticity (x, y) that
is measured at step 2 is obtained.
8.
Press the MEMORY key and save the adjustment
value.
2-5-2. LOW Mode of INPUT-A
1.
Input the 80 IRE flat field signal to the INPUT-A
connector.
2-10
VPL-DS100
2-6. Memory Structure
Memory Structure
CPU internal ROM :
384 K byte Flash Memory
CPU internal RAM :
30 K byte
External NVM memory :
8 K byte EEPROM
NT358/443/BW60
15k RGB
Component (15k)
Double-speed component
HDTV (YPbPr)
HDTV (GBR) 
includ.double-speed
PAL/PAL-M/N/
SECAM/BW50
NT358/443/BW60
15k RGB
Component (15k)
Double-speed component
HDTV (YPbPr)
HDTV (GBR) 
includ.double-speed
PAL/PAL-M/N/
SECAM/BW50
Set Memory
Set Memory
Set Memory
Status Memory
Picture Memory
Chroma Memory
Channel Memory
Image Flip Memory
Status
Memory
No. 01
No. 02
No. 03
No. 04
No. 05
...
No. 99
Picture
Memory
Chroma
Memory
Chroma
Memory
Status
Memory
No. 01
No. 02
No. 03
No. 04
No. 05
...
...
No. 99
No. 101
No. 120
Input-A
Preset
Input-A
Preset
Input-A
User
Video
Dynamic
Standard
S
Video
Dynamic
Standard
Input-A
Dynamic
Standard
W/B
Memory
Channel
Memory
Computer
Others
High
Low
High
Low
W/B
Memory
Computer
Others
High
Low
High
Low
W/B
Memory
High
Low
Picture
Memory
Video
Dynamic
Standard
S
Video
Dynamic
Standard
Input-A
Dynamic
Standard
Video
S Video
Input-A
Channel
Memory
Video
S Video
Input-A
CPU ROM
Initialize
Memory
Active memory copy
External NVM
CPU RAM
Image Flip
Memory
Up/Down inversionis
impossible
Up/Down inversionis
possible
Up/Down inversionis
possible
Up/Down inversionis
impossible
Image Flip
Memory
2-11
VPL-DS100
Memory structure consists of the followings.
1
Set memory
2
Status memory
3
Picture memory
4
Chroma memory
5
W/B memory
6
Channel memory
7
Image Flip memory
*
 The gamma memory is realized by giving offset to Contrast and Brightness output values to the devices in the gamma mode function.
 Flow of data is described briefly. When the power plug is connected to the wall outlet for the first time
(Standby state), all data that are stored in the internal ROM are written in the NVM(non-volatile memo-
ry). When the POWER is turned ON, all the status memory data and other memory data that are required
for the present picture are selected from each memory block and expanded in the internal RAM.
 When any adjustment is performed at this moment, the adjustment data(user mode items) are written in
the NVM(Service/Special Service item) automatically triggered by the memory operation.
 The adjustment items(W/B, Device Adjust) that can be adjusted in the Service Mode or in the Special
Service Mode, are memorized in the NVM at the time when the user performs adjustment and performs
the memory operation. Note that the factory adjustment data will be lost at this moment.
3-1
VPL-DS100
Section 3
Semiconductors
IC
24LC21AT/SN
CY25023SZC-1T
HN58X24256FPIZ
M24C64-WMN6T(B)
SI4403DY-T1
ST24FC21M6TR
TC7WH125FK(TE85R)
TC7WH34FU(TE12R)
UPC393G2
UPC393G2-E2
1
TOP VIEW
8pin  SOP
2SK219F04
1
3
2
ADXL202JE-REEL
1
2
3
4
8
5
INDEX
6
7
AIC1084-PEJTR
1
2
3
AIC1117A-18PYJTR
AIC1117A-33PYJTR
AIC1117A-50PYJTR
1
2
3
BA00ASFP-E2
GND
1 : IN
2 : GND
3 : OUT
1
2
3
BA00AST
BA00AST-V5
1
2 3
4 5
BA09FP-E2
VCC
GND
OUT
BA6288FS-E2
MC74HC4052ADTR2
TC74HC4052AFT(EL)
TPA2001D1PWR
1
TOP VIEW
16pin  SOP
CXA2171AQ
CXA2171AQ-T6
CXA7005R-T4
1
TOP VIEW
48pin  QFP
CXD3536R
1
TOP VIEW
176pin  QFP
HD64F2376VFQ33V
1
TOP VIEW
144pin QFP
LMC7101BIM5X
TK11125CSCL-G
4
5
2
1
3
LTC1772CS6
1
TOP VIEW
6pin  SOP
M52347FP-TE
SN74AHCT541PWR
SN74LV244APWR
TC74VHCT540AFT(EL)
TDA7309D013TR
1
TOP VIEW
20pin  SOP
SN74LV00APWR
SN74LV02APWR
TC74LCX125FT(EL)
1
TOP VIEW
14pin  SOP
MCZ3001U
1
TOP VIEW
32pin  SOP
MX29LV800ATTC-70G-
751PW100
1
TOP VIEW
48pin SOP
PW168A-05VL
BOTTOM VIEW
1
A
352pin PGA
PW2200-05L
PW2200A-05L
1
TOP VIEW
208pin QFP
RS-140-T
1
2
3
4
TK11900MTL
1
6pin  CHIP
TL431CPK-E2
1
TOP VIEW
8pin  DIP
S-80928CNMC-G8YT2G
1
2
3
4
5
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