Sony DCR-TRV900 Service Manual ▷ View online
10
2. CAMERA CIRCUIT
2-1. Record Mode
Dichroic Prism
The incident light that is introduced from the lens block, is adjusted of its amount
by iris and enters the dichroic prism.
The incident light is separated into the three primary spectrum of R, G and B.
CCD Imager (IC100, IC101, IC102)
The CCD imager is driven by the pulses (V1 to V3, H1, H2 and PG) that are
supplied from the timing generator.
The incident light to the CCD imager is converted to the electrical signals of R,
G and B.
Sample-and-hold, AGC (IC203)
The output signal from the CCD imager is sample-and-held by the signals
(XSHIP, XSHD) that are supplied from the timing generator. The sample-and-
hold is performed in order to ensure operation of the A/D conversion at the latter
circuit. When the signal amplitude after sample-and-hold is small, the signal is
amplified by the AGC amplifier to obtain the sufficient amplitude.
The right end and the left end of B signal output that is introduced to this IC
from the CCD imager, is horizontally inverted due physical structure of the
dichroic prism.
A/D Converter (IC206, IC205, IC207)
The R. G. B. video signal that are output from the sample-and-hold (IC203) are
converted from analog signal to 10-bit digital signal in accordance with the
sampling frequency which is generated by the timing generator.
Digital Camera Processor (IC300)
The B channel signal is stored in a line-memory in this processor where the
right end and the left end of B signal are inverted to the correct sequence. Then
the R. G. B. signals receive the white balance adjustment, gamma correction
and are mixed to the Y signal and the color difference signal.
Timing Generator (IC204)
The master frequency of 27 MHz is frequency divided-by-2 and is used as the
timing pulse of the camera system.
AE (Auto Exposure)
Amplitude of the video signal that is input to the digital camera processor (IC300)
is detected. The output signal of the amplitude detection is sent to the camera
controller (IC302) that controls the iris drive amplifier (IC501) so that the lens
iris is controlled in accordance with the signal amplitude.
ND Filter
The same detection circuit as the AE operation, is used for the ND control.
When an ND filter needs to be inserted in the optical path, the message “ND
ON” is displayed on the LED and LCD screens.
11
Camera Block Diagram
12
2-2. Progressive System
2-2-1. Principle of Progressive System
What is the progressive system?
In the conventional interlaced TV system, a video frame consists of the two fields that are alternately displayed one after another. It means that
the half the entire picture elements is displayed at a moment.
On the contrary, the progressive system displays all the picture elements (entire frame) at a time.
∗
1: One entire frame (amount of picture elements
that is equivalent to an entire video frame) of
video output signal from the CCD imager is
written in the DRAM (IC752).nventional inter-
laced TV sy
∗
2: The video signat are alternately displayedal that
is written in the DRAM (IC752) takes the two
outputs. One outpentire picture elements is diut
goes to HONEY (IC756) and the other output
goes to DRAM (IC752).ontrary, the progressive
sy
∗
3: The odd and evame) at a time.en signals that are
read out from the DRAM (IC752) as described
in the previous step
∗
2, are written and read to
and from the VFD (IC1501) simultaneously.
Functions of the DRAM and HONEY that are shown
on the monitor display. are illustrated in the figure in
the left.
CCD
OUT
OUT
VD
HONEY
DRAM
HONEY
+
IC752
OUT
VFD
RAM
VFD
OUT
VD
WRITE
READ
1st
2nd
READ
WRITE
A1
B1
A2
B2
B1
A2
B2
IC752
WRITE
READ
WRITE
Write
∗
2 Read
∗
1
∗
3
A1B1A2B2...........
A1A2...
B1B2...
13
2-2-2. Loading the Progressive Picture to Memory
(1) The video output signal from the camera block is stored in the DRAM (IC752)
as many as picture elements of one frame. The video signal is converted
here to the VGA (640
×
460) size.
(2) When the video signal equivalent to picture elements of one frame, is stored,
it is read by the HONEY (IC756).
(3) The read-out data is sent to the JPEG (IC757).
(4) The data is then compressed in the JPEG (IC757) and is sent to the DRAM
(IC758).
(5) The data from DRAM (IC758) is added by the header information and the
directory that are supplied from the DS controller I the PC card I/F (IC701).
The added information is stored in the PC card.
2-2-3. Reading the Progressive Picture from Memory to VFD
(6) The compressed data that is output from the PC card, takes the two paths.
The picture information only of the compressed data, is sent to the DRAM
(IC758). The header information and directory only of the compressed data,
is sent to the DS controller.
(7) The picture information is expanded by the JPEG (IC757).
(8) The read-out data from the PC card, is sent to the DRAM (IC752) through
the HONEY (IC756).
(9) The picture information is sent to the VFD (IC1501) through the HONEY
(IC756).
Signal processing block diagram of the still picture
(1)
IC756
HONEY
JPEG
DRAM (4M)
IC701
IC758
IC757
IC752
IC751
DRAM (16M)
(2)
(3)
(4)
(5)
(6)
DATA BUS
ADDRESS BUS
from CAM, BBI,
VFD
VFD
PC card I/F
(9)
(8)
(7)
IC1501
VFD
DS controller
(SH2)
Recording medium
(PC card)
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