DOWNLOAD Sony DVP-CX985V Service Manual ↓ Size: 10.78 MB | Pages: 127 in PDF or view online for FREE

Model
DVP-CX985V
Pages
127
Size
10.78 MB
Type
PDF
Document
Service Manual
Brand
Device
DVD
File
dvp-cx985v.pdf
Date

Sony DVP-CX985V Service Manual ▷ View online

101
DVP-CX985V
Pin No.
Pin Name
I/O
Description
49
AVDREQ1
I
Request signal input from the AV decoder
50
AVDDACK1
O
Acknowledge signal output to the AV decoder
51
XIFCS
O
Chip select signal output to the interface controller
52
VSS
Ground terminal
53
X1
O
System clock output terminal (16.5 MHz)
54
X0
I
System clock input terminal (16.5 MHz)
55
VCC
Power supply terminal (+3.3V)
56
(CKSW1)
O
Not used
57
(OCSW1)
O
Not used
58
XROMCS
O
Chip select signal output to the flash memory
59
XRAMCS
O
Chip select signal output to the S-RAM
60, 61
XAVCS0, XAVCS1
O
Chip select signal output to the AV decoder
62
XARPCS
O
Chip select signal output to the DSP
63
XSDSPCS
O
Chip select signal output to the DSP
64
VCCI
Power supply terminal (+1.8V)
65
XGACS
O
Chip select signal output to the mechanism controller
66
(NC)
O
Not used
67
XWAIT
I
Wait signal input from the DSP and AV decoder
68
TEST (H)
I
Input terminal for the test (normally: fixed at “H”)
69
TEST
I
Input terminal for the test
70
XRD
O
Read enable signal output to the flash memory, S-RAM, DSP, AV decoder and mechanism
controller
71
XWRH
O
High byte write enable signal output to the flash memory, S-RAM, DSP, AV decoder and
mechanism controller
72
XWRL
O
Low byte write enable signal output to the S-RAM
73
XNMI
I
Not used
74
VCCI
Power supply terminal (+1.8V)
75
VSS
Ground terminal
76
XRESET
I
Reset signal input from the interface controller    “L”: reset
77
CPUCK
O
Master clock (33 MHz) signal output to the mechanism controller
78
SMUTE
O
Soft muting control signal output to the DSD decoder
79
XDACS
O
Chip select signal output to the D/A converter
80
XADSPCS
O
Chip select signal output to the audio DSP
81
48/44.1K
O
PLL frequency control signal output to the clock generator
82
XLDON
O
Laser diode control signal output to the RF amplifier
83
MAMUTE
O
Audio muting control signal output terminal
84
XSRWE
O
Write enable signal to the S-RAM
85 to 100
HD0 to HD15
I/O
Two-way data bus terminal
101
VSS
Ground terminal
102 to 109
HA0 to HA7
O
Address signal output terminal
110
VCC
Power supply terminal (+3.3V)
111 to 118
HA8 to HA15
O
Address signal output terminal
119
VSS
Ground terminal
120
HA16
O
Address signal output terminal
102
DVP-CX985V
 MB BOARD   IC201   SP3726A (CD/DVD/SACD RF AMP, FOCUS/TRACKING ERROR AMP)
Pin No.
Pin Name
I/O
Description
1, 2
RFIP, RFIN
I
RF signal input from the optical pick-up block
3
CP
Tracking low-pass filter terminal
4
WIN
I
Wobble detection signal input terminal    Not used
5
WPP
O
Wobble push-pull signal output terminal    Not used
6
CN
Tracking low-pass filter terminal
7 to 10
A2 to D2
I
Photo detector interface input from the optical pick-up block
(AC coupled input for the DPD and wobble)
11 to 14
D to A
I
Photo detector interface input from the optical pick-up block (main)
15, 16
E, F
I
Photo detector interface input from the optical pick-up block (sub)
17
SIGDET B
O
Signal detection signal output to the DSP
18
INTR
I
Interruption control signal input from the DSP
19
VC
O
Reference voltage (+2.5V) output to the optical pick-up block
20
VPB
Power supply terminal (+5V) ( for servo block)
21
PGSELO
O
PDIC gain selection signal output to the optical pick-up block
22
PD
I
Automatic power control signal input from the optical pick-up block
23
VNB
Ground terminal (for servo block)
24
LDSELO
O
Automatic power control laser diode selection signal output to the optical pick-up block
25
DVDLD
O
DVD automatic power control signal output terminal
26
CDLD
O
CD automatic power control signal output terminal
27
LDONB
I
Laser diode output control signal input from the system controller
28
MEVO
O
Envelope signal output terminal for mirror
29
MIN
I
RF signal input terminal for mirror
30
MP
Mirror top hold terminal
31
MB
Mirror bottom hold terminal
32
MLPF
Mirror low-pass filter terminal
33
MIRR
O
Mirror signal output to the DSP
34
BYP2
Servo AGC gain control terminal
35
PII
I
Pull-in signal input terminal
36
PI
O
Pull-in signal output to the DSP
37
TZC
O
Tracking zero crossing signal output to the DSP
38
DFT
O
Defect signal output to the DSP
39
VCI
I
Reference voltage input from the motor/coil driver
40
TZIN
I
Tracking zero crossing signal input terminal
41
TE
O
Tracking error signal output to the DSP
42
FE
O
Focusing error signal output to the DSP
43
TPH
Pull-in top hold terminal
44
MON
O
Monitor signal output to the DSP
45
SRD
O
Serial data output to the DSP
46
SWD
I
Serial data input from the DSP
47
SCLK
I
Serial clock signal input from the DSP
48
SDEN
I
Serial data enable signal input from the DSP
49
V33
Power supply terminal (+3.3V) (for CMOS output buffers)
50
RX
I
Reference resistor input terminal
51
TPA
RF top hold terminal
52
MEV
RF bottom envelope terminal
103
DVP-CX985V
Pin No.
Pin Name
I/O
Description
53
VNA
Ground terminal (for RF block and serial port)
54, 55
FNN, FNP
O
Differential filter normal signal output terminal
56, 57
DIP, DIN
I
Analog signal input terminal for RF single buffer
58
BYP
RF AGC gain control terminal
59
SIGO
O
Single-ended RF signal output to the DSP and DSD decoder
60
VPA
Power supply terminal (+5V) (for RF block and serial port)
61, 62
AIP, AIN
I
AGC amplifier signal input terminal
63, 64
ATON, ATOP
O
Differential attenuator signal output terminal
104
DVP-CX985V
 MB BOARD  IC301  CXD9703R (DIGITAL SIGNAL PROCESSOR, DIGITAL SERVO PROCESSOR)
Pin No.
Pin Name
I/O
Description
1
VSS
Ground terminal (for digital system)
2 to 9
A0 to A7
I
Address signal input terminal
10
VDD1.8V
Power supply terminal (+1.8V) (for digital system)
11
XINT
O
Interrupt signal output to the system controller
12
HCS
I
Chip select signal input from the system controller
13
TESTK0
I
Input terminal for the test (normally: fixed at “L”)
14
VSS
Ground terminal (for digital system)
15
PDM0
O
Tracking coil drive signal output terminal
16
TESTK1
I
Input terminal for the test (normally: fixed at “L”)
17
PDM1
O
Tracking coil drive signal output terminal
18
TESTK2
I
Input terminal for the test (normally: fixed at “L”)
19
VDD3.3V
Power supply terminal (+3.3V) (for digital system)
20
PDM2
O
Focus coil drive signal output terminal
21
TESTK3
I
Input terminal for the test (normally: fixed at “L”)
22
PDM3
O
Focus coil drive signal output terminal
23
VSS
Ground terminal (for digital system)
24
XWR
I
Write enable signal input from the system controller
25
XRD
I
Read enable signal input from the system controller
26
XINT
O
Interrupt signal output to the system controller
27
XCS
I
Chip select signal input from the system controller
28
XWAIT
O
Wait signal output to the system controller
29
XMWR
O
Write enable signal output to the D-RAM
30
XCAS
O
Column address strobe signal output to the D-RAM
31
XRAS
O
Row address signal output to the D-RAM
32, 33
MDS0, MDS1
O
Spindle motor drive signal output terminal
34
VDD1.8V
Power supply terminal (+1.8V) (for digital system)
35
VSS
Ground terminal (for digital system)
36 to 43
MD0 to MD7
I/O
Two-way data bus with the D-RAM
44
VDD3.3V
Power supply terminal (+3.3V) (for digital system)
45
VSS
Ground terminal (for digital system)
46 to 53
MD8 to MD15
I/O
Two-way data bus with the D-RAM
54
VDD1.8V
Power supply terminal (+1.8V) (for digital system)
55
LOCK
O
EFM lock detection signal output terminal    Not used
56
DOUT
O
Digital audio data output to the AV decoder and audio DSP
57
SDCK
O
Stream data bus clock signal output to the AV decoder and DSD decoder
58
XSHD
O
Stream data bus header flag signal output to the AV decoder and DSD decoder
59
XSRQ
I
Stream data bus request signal input from the AV decoder and DSD decoder
60
VSS
Ground terminal (for digital system)
61
XRESET
I
Reset signal input from the system controller    “L”: reset
62
VDD3.3V
Power supply terminal (+3.3V) (for digital system)
63
XSAK
O
Stream data bus acknowledge signal output to the AV decoder and DSD decoder
64
SDEF
O
Stream data bus error flag signal output to the AV decoder and DSD decoder
65 to 74
MA0 to MA9
O
Address signal output to the D-RAM
75
VSS
Ground terminal (for digital system)
76
VDD1.8V
Power supply terminal (+1.8V) (for digital system)
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