Sony DAV-C770 / HCD-C770 / HCD-C990 Service Manual ▷ View online
93
HCD-C770/C990
Pin No.
Pin Name
I/O
Description
46
VDDE
—
Power supply terminal (+3.3V)
47
WMD1
I
S-RAM wait mode setting terminal Fixed at “H” in this set
48
VSS
—
Ground terminal
49
WMD0
I
S-RAM wait mode setting terminal Fixed at “L” in this set
50
PAGE2
O
Page selection signal output terminal Not used
51
VSS
—
Ground terminal
52, 53
PAGE1, PAGE0
O
Page selection signal output terminal Not used
54
BOOT
I
Boot mode control signal input terminal Not used
55
BTACT
O
Boot mode state display signal output terminal Not used
56
BST
I
Boot trap signal input from the system controller
57
MOD1
I
PLL input frequency selection signal input terminal
“L”: 384fs, “H”: 256fs (fixed at “H” in this set)
“L”: 384fs, “H”: 256fs (fixed at “H” in this set)
58
MOD0
I
Mode setting terminal “L”: single chip mode, “H”: use prohibition (fixed at “L” in this set)
59
EXLOCK
I
PLL lock error and data error flag input from the digital audio interface IC
60
VDDI
—
Power supply terminal (+2.6V)
61
VSS
—
Ground terminal
62, 63
A17, A16
O
Address signal output terminal Not used
64 to 66
A15 to A13
O
Address signal output to the S-RAM
67
GP10
O
L/R sampling clock signal (44.1 kHz) output to the D/A converter and stream processor
68
GP9
O
Decode signal output to the system controller
69
GP8
I
Bit 1 input terminal of channel status from the digital audio interface IC
70
VDDI
—
Power supply terminal (+2.6V)
71
VSS
—
Ground terminal
72 to 75
D15 to D12
I/O
Two-way data bus with the S-RAM
76
VDDE
—
Power supply terminal (+3.3V)
77 to 80
D11 to D8
I/O
Two-way data bus with the S-RAM
81
VSS
—
Ground terminal
82 to 85
A9, A12 to A10
O
Address signal output to the S-RAM
86
TDO
O
Simple emulation data output terminal Not used
87
TMS
I
Simple emulation data input start/end detection signal input terminal Not used
88
XTRST
I
Simple emulation asychronous break input terminal Not used
89
TCK
I
Simple emulation clock signal input terminal Not used
90
TDI
I
Simple emulation data input terminal Not used
91
VSS
—
Ground terminal
92 to 97
A8 to A3
O
Address signal output to the S-RAM
98, 99
D7, D6
I/O
Two-way data bus with the S-RAM
100
VDDI
—
Power supply terminal (+2.6V)
101
VSS
—
Ground terminal
102 to 105
D5 to D2
I/O
Two-way data bus with the S-RAM
106
VDDE
—
Power supply terminal (+3.3V)
107, 108
D1, D0
I/O
Two-way data bus with the S-RAM
109, 110
A2, A1
O
Address signal output to the S-RAM
111
VSS
—
Ground terminal
112
A0
O
Address signal output to the S-RAM
113
PM
I
PLL reset signal input from the system controller “L”: reset
114
SDI3
I
Rear L-ch and R-ch audio serial data input from the digital audio processor
94
HCD-C770/C990
Pin No.
Pin Name
I/O
Description
115
SDI4
I
Audio serial data input terminal Not used
116
SYNC
I
Synchronous/asychronous selection signal input terminal
“L”: Synchronous, “H”: asynchronous (fixed at “H” in this set)
“L”: Synchronous, “H”: asynchronous (fixed at “H” in this set)
117 to 119
VSS
—
Ground terminal
120
VDDI
—
Power supply terminal (+2.6V)
95
HCD-C770/C990
•
DVD BOARD IC701 CXD1882R (DVD DECODER)
Pin No.
Pin Name
I/O
Description
1, 2
D5, D6
I/O
Two-way data bus with the mechanism controller
3
VSS
—
Ground terminal (digital system)
4
D7
I/O
Two-way data bus with the mechanism controller
5
A0
I
Address signal input from the mechanism controller
6
VDD
—
Power supply terminal (+3.3V) (digital system)
7
A1
I
Address signal input from the mechanism controller
8
VDD5V
—
Power supply terminal (+5V)
9 to 14
A2 to A7
I
Address signal input from the mechanism controller
15
VSS
—
Ground terminal (digital system)
16
XWAIT
O
Wait signal output terminal Not used
17
XRD
I
Read strobe signal input from the mechanism controller
18
XWR
I
Write strobe signal input from the mechanism controller
19
XCS
I
Chip select signal input from the mechanism controller
20, 21
XINT0, XINT1
O
Interrupt signal output to the mechanism controller
22
VDD
—
Power supply terminal (+3.3V) (digital system)
23
XHRS
I
Not used
24
HDB7
O
Stream data signal output to the DSD decoder and DVD system processor
25
VSS
—
Ground terminal (digital system)
26
HDB8
O
Error flag signal output to the DSD decoder and DVD system processor
27
HDB6
O
Stream data signal output to the DSD decoder and DVD system processor
28
VDDS
—
Power supply terminal (+5V) (digital system)
29
HDB9
O
Not used
30
HDB5
O
Stream data signal output to the DSD decoder and DVD system processor
31
HDBA
O
Not used
32
HDB4
O
Stream data signal output to the DSD decoder and DVD system processor
33
VSS
—
Ground terminal (digital system)
34
HDBB
O
Not used
35
HDB3
O
Stream data signal output to the DSD decoder and DVD system processor
36
VDD
—
Power supply terminal (+3.3V) (digital system)
37
HDBC
O
Not used
38
VDDS
—
Power supply terminal (+5V) (digital system)
39
HDB2
O
Stream data signal output to the DSD decoder and DVD system processor
40
HDBD
O
Not used
41
HDB1
O
Stream data signal output to the DSD decoder and DVD system processor
42
VSS
—
Ground terminal (digital system)
43
HDBE
O
Not used
44
HDB0
O
Stream data signal output to the DSD decoder and DVD system processor
45
HDBF
O
Not used
46
XSAK
O
Serial data effect flag signal output to the DSD decoder and DVD system processor
47
VDDS
—
Power supply terminal (+5V) (digital system)
48
XDCK
O
Serial data transfer clock signal output to the DSD decoder and DVD system processor
49
XSHD
O
Header flag signal output to the DSD decoder
50
VDD
—
Power supply terminal (+3.3V) (digital system)
51
REDY
O
Not used
52
VSS
—
Ground terminal (digital system)
96
HCD-C770/C990
Pin No.
Pin Name
I/O
Description
53
XSRQ
I
DVD mode: Serial data request signal input from the DVD system processor
SACD mode: Serial data request signal input from the DSD decoder
SACD mode: Serial data request signal input from the DSD decoder
54
HINT
O
Not used
55
XS16
O
Not used
56
HA1
I
Not used
57
XPDI
I/O
Not used
58
VDDS
—
Power supply terminal (+5V) (digital system)
59, 60
HA0, HA2
I
Not used
61
VSS
—
Ground terminal (digital system)
62, 63
HCS0, HCS1
I
Not used
64
VDD
—
Power supply terminal (+3.3V) (digital system)
65
DASP
I/O
Not used
66 to 69
MDB0 to MDB3
I/O
Two-way data bus with the D-RAM
70
VSS
—
Ground terminal (digital system)
71
MDB4
I/O
Two-way data bus with the D-RAM
72
VDD5V
—
Power supply terminal (+5V)
73 to 75
MDB5 to MDB7
I/O
Two-way data bus with the D-RAM
76
XMWR
O
Write enable signal output to the D-RAM
77
VDD
—
Power supply terminal (+3.3V) (digital system)
78
XRAS
O
Row address strobe signal output to the D-RAM
79, 80
MA0, MA1
O
Address signal output to the D-RAM
81
VSS
—
Ground terminal (digital system)
82 to 87
MA2 to MA7
O
Address signal output to the D-RAM
88
VDD
—
Power supply terminal (+3.3V) (digital system)
89
MA8
O
Address signal output to the D-RAM
90
VSS
—
Ground terminal (digital system)
91
MA9
O
Address signal output to the D-RAM
92
MNT1
O
EEPROM ready signal output to the mechanism controller
93
MNT2
O
Operation clock signal output for PSP physical disc mark detection to DSD decoder
94
XMOE
O
Output enable signal output to the D-RAM
95
XCAS
O
Column address strobe signal output to the D-RAM
96, 97
MDB8, MDB9
I/O
Two-way data bus with the D-RAM
98
VSS
—
Ground terminal (digital system)
99
MDBA
I/O
Two-way data bus with the D-RAM
100
VDD
—
Power supply terminal (+3.3V) (digital system)
101, 102
MDBB, MDBC
I/O
Two-way data bus with the D-RAM
103
VDD5V
—
Power supply terminal (+5V)
104 to 106 MDBD to MDBF
I/O
Two-way data bus with the D-RAM
107
GFS
O
Guard frame sync signal output to the mechanism controller
108
VSS
—
Ground terminal (digital system)
109
APEO
O
Absolute phase error signal output
110
VDD
—
Power supply terminal (+3.3V) (digital system)
111
DASYO
O
RF binary signal output
112
GNDA5
—
Ground terminal (analog system)
113, 114
ASF1, AFS2
—
Filter connected terminal for selection the constant asymmetry compensation
115
DASYI
I
Analog signal input after integrated from the RF binary signal
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