Sony BDP-N460 Service Manual ▷ View online
5-6
BDP-N460
A
B
C
D
E
F
G
H
1
2
5
4
3
6
MB-130
1-878-828-11
There are a few cases that the part isn’t mounted in this model is printed on this diagram.
: Uses unleaded solder.
5-6. MB-130 BOARD (MAIN) PRINTED WIRING BOARD (SIDE B) • See page 2-5 for circuit boards location.
- Ref. No.: MB-130 board; 10,000 series -
MB-130 BOARD (SIDE B)
D303 B-2
D304 B-6
D305 C-6
D306 B-1
D304 B-6
D305 C-6
D306 B-1
IC303 F-4
IC304 E-2
IC305 F-3
IC308 A-2
IC309 B-2
IC310 B-6
IC601 C-1
IC602 C-1
IC701 E-3
IC703 E-3
IC704 F-3
IC802 F-5
IC803 F-4
IC805 G-5
IC1001 F-2
IC1101 F-1
IC304 E-2
IC305 F-3
IC308 A-2
IC309 B-2
IC310 B-6
IC601 C-1
IC602 C-1
IC701 E-3
IC703 E-3
IC704 F-3
IC802 F-5
IC803 F-4
IC805 G-5
IC1001 F-2
IC1101 F-1
Q304 B-2
Q305 B-2
Q306 B-6
Q501 G-5
Q502 G-5
Q503 G-6
Q702 G-3
Q804 F-3
Q805 G-3
Q806 F-3
Q809 F-4
Q810 F-4
Q1101 F-1
Q305 B-2
Q306 B-6
Q501 G-5
Q502 G-5
Q503 G-6
Q702 G-3
Q804 F-3
Q805 G-3
Q806 F-3
Q809 F-4
Q810 F-4
Q1101 F-1
5-7E
BDP-N460
There are a few cases that the part isn’t mounted in this model is printed on this diagram.
: Uses unleaded solder.
5-7. USB-021 BOARD (USB (REAR)) PRINTED WIRING BOARD
- Ref. No.: USB-021 board; 20,000 series -
• See page 2-5 for circuit boards location.
USB-021 BOARD (SIDE B)
CN361 A-2
CN362 A-2
CN362 A-2
USB-021 BOARD (SIDE A)
A
1
2
USB-021
1-879-807-11
A
1
2
USB-021
1-879-807-11
USB-021 BOARD (SIDE B)
There are a few cases that the part isn’t mounted in this model is printed on this diagram.
: Uses unleaded solder.
5-8. USF-002 BOARD (USB (FRONT)) PRINTED WIRING BOARD
- Ref. No.: USF-002 board; 20,000 series -
• See page 2-5 for circuit boards location.
USF-002 BOARD (SIDE B)
CN371 A-1
CN372 A-1
CN372 A-1
USF-002 BOARD (SIDE A)
USF-002 BOARD (SIDE B)
A
1
2
USF-002
1-879-808-11
A
1
2
USF-002
1-879-808-11
6-1
BDP-N460
SECTION 6
IC PIN FUNCTION DESCRIPTION
6-1. MAIN SYSTEM CONTROL PIN FUNCTION (MB-130 BOARD IC101: CXD9975GB)
Pin
Symbol
Type
Description
A1 N.U.
I/O
Not
used
A2
N.U. I/O
Not
used
A3
ETTXEN
O
Transmit Enable to the PHY
A4
ETTXD1
O
Transmit Data to the PHY
A5
ETRXD1
I
Receive Data from the PHY
A7
MCIN
I/O
XVMUTE (Video Mute ON = “0”)
A8
AOSDATA4
O
Audio Out Serial Data 4
A10
AOMCK
I/O
Audio Out Master Clock
A11
CH2_P
Analog
HDMI TX Data 2 Differential pair (P)
A12
CH1_P
Analog
HDMI TX Data 1 Differential pair (P)
A13
CH0_P
Analog
HDMI TX Data 0 Differential pair (P)
A14
CLK_P
Analog
HDMI TX Clock Differential pair (P)
A15
N.U.
Analog
Not used
A16
XTALO
O
27MHz Crystal Out
A17
AVDD33_XTAL
Power
3.3V Analog Power for XTAL
A18
AVDD33_VDPLL
Power
3.3V Analog Power for VDPLL
A20
IOG
Analog
DAC Output
A21
IOC
Analog
DAC Output
A22
DACVREF
Analog
DAC Reference Voltage
A23
SFCK
I/O
Serial Flash Clock
A24
NFWEN
I/O
NAND Flash Write Enable
A25
NFCEN
I/O
NAND Flash Chip Enable
A26
NFREN
I/O
NAND Flash Read Enable
B1
SD2D1
I/O
FORMAT1 (480 = “0” 720,1080 = “1”
B2
SD2D0
I/O
NAND_WP (Nand Flash Write Protect)
B3
ETTXD3
O
Transmit Data to the PHY
B4
ETTXD0
O
Transmit Data to the PHY
B5
ETRXD0
I
Receive Data from the PHY
B6
ETCRS
I
Carrier Sense from the PHY
B7
ETMDIO
I/O
Management Data Input/Output from/to the MDIO pin
B8
N.U.
O
Not used
B9
AOSDATA2
O
Audio Out Serial Data 2
B10
AOBCK
I/O
Audio Out Bit Clock
B11
CH2_M
Analog
HDMI TX Data 2 Differential pair (M)
B12
CH1_M
Analog
HDMI TX Data 1 Differential pair (M)
B13
CH0_M
Analog
HDMI TX Data 0 Differential pair (M)
B14
CLK_M
Analog
HDMI TX Clock Differential pair (M)
B15
EXT_RES
Analog
HDMI Reference Voltage
B16
XTALI
I
27MHz Crystal In
B17
AVDD33_APLL
Power
3.3V Analog Power for APLL
B18
AVDD33_ARMPLL
Power
3.3V Analog Power for ARMPLL
B19
IOR
Analog
DAC Output
B20
IOB
Analog
DAC Output
B21
IOY
Analog
DAC Output
B22
N.U.
I/O
Not used
B23
SFCS
I/O
Serial Flash Chip Select
B24
NFALE
I/O
NAND Flash Address Latch Enable
B25
NFD1
I/O
NAND Flash Data Input/Output Bit 1
B26
NFD2
I/O
NAND Flash Data Input/Output Bit 2
C1
SD2D3
I/O
ETHER_PCONT (Ethernet Power Control)
C2
SD2D2
I/O
UPG_STATUS (Upgrade Status)
C3
ETCOL
I
Collision Detect from the PHY
C4
ETTXD2
O
Transmit Data to the PHY
C5
ETRXDV
I
Receive Data Valid Signal from the PHY
C6
ETRXER
I
Receive Error Signal from the PHY
C7
AMUTE
O
Audio DAC Mute ( XAMUTE, L= MUTE)
C8
SPDIF (5V)
O
SPDIF Digital Audio Out
C9
AOSDATA1
O
Audio Out Serial Data 1
C10
HDMISD
I/O
HDMI I2C Data
6-2
BDP-N460
Pin
Symbol
Type
Description
C11
AVSS_HDMI
Ground
Analog Ground
C12
AVDD12_HDMI
Power
1.2V Analog Power
C13
AVDD33_HDMI
Power
3.3V Analog Power
C14
AVDD33_HDMI
Power
3.3V Analog Power
C15
AVSS33_XTAL
Ground
Analog GND for XTAL
C16
N.C.
Analog
Not Used
C17
AVDD33_SYSPLL2
Power
3.3V Analog Power for SYSPLL
C18
AVDD33_VDACR
Power
3.3V Analog Power
C19
AVDD33_VDACBG
Power
3.3V Analog Power
C20
N.C.
Analog
Not Used
C21
FS
Analog
DAC Fullscale
C22
SFDI
I/O
Data Input from Serial Flash
C23
NFCLE
I/O
NAND Flash Command Latch Enable
C24
NFRBN
I/O
NAND Flash Ready/Busy
C25
NFD5
I/O
NAND Flash Data Input/Output Bit 5
C26
NFD6
I/O
NAND Flash Data Input/Output Bit 6
D1
N.U.
I/O
Not used
D2
N.U.
I/O
Not used
D3
N.U.
I/O
Not used
D4
DVSS Ground
Digital
Ground
D5
ETTXCLK
I
Transmit Clock from the PHY
D6
ETRXD3
I
Receive Data from the PHY
D7
ETTXER
O
Transmit Error Signal to the PHY
D8
DVCC3IO
Power
3.3 V Digital Power
D9
N.U.
I/O
Not used
D10
AOLRCK
I/O
Audio Out Left-Right Clock
D11
CEC
I/O
HDMI CEC
D12
AVSS_HDMI
Ground
Analog Ground
D13
AVSS_HDMI
Ground
Analog Ground
D14
AVDD12_SYSPLL
Power
1.2V Analog Power for SYSPLL
D15
N.C.
Analog
Not Used
D16
AVSS33_SYSPLL2
Ground
Analog Ground for SYSPLL
D17
AVSS33_VDPLL
Ground
Analog Ground for DVPLL
D18
AVDD33_VDACY
Power
3.3V Analog Power
D19
AVSS33_VDACY
Ground
Analog Ground
D20
AVSS33_VDACBG
Ground
Analog Ground
D21
SFDO
I/O
Data Output to Serial Flash
D22
NFD0
I/O
NAND Flash Data Input/Output Bit0
D23
NFD3
I/O
NAND Flash Data Input/Output Bit 3
D24
NFD7
I/O
NAND Flash Data Input/Output Bit 7
D25
BRCLK1
O
DRAM Clock 1
D26
BRCLKB1
O
DRAM Clock 1 Inverted
E1
N.U.
I/O
Not used
E2
N.U.
I/O
Not used
E3
N.U.
I/O
Not used
E4
PMCD1N
I/O
External Interrupt 1
E5
DVSS Ground
Digital
Ground
E6
ETRXCLK
I
Receive Clock from the PHY
E7
ETRXD2
I
Receive Data from the PHY
E8
ETMDC
O
Management Data Clock to the PHY
E9
DVCC3IO
Power
3.3 V Digital Power
E10
AOSDATA0
O
Audio out serial data 0
E11
HDMISCK
I/O
HDMI I2C Clock
E12
HTPLG
I/O
HDMI Hot Plug
E14
AVSS12_SYSPLL
Ground
Analog GND for SYSPLL
E16
AVSS33_APLL
Ground
Analog Ground for APLL
E17
AVSS33_ARMPLL
Ground
Analog Ground for ARMPLL
E18
AVSS33_VDACR
Ground
Analog Ground
E19
N.U.
I/O
Not used
E20
DVCC3IO
Power
3.3 V Digital Power
E21
DVCC3IO
Power
3.3 V Digital Power
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