Sony AVD-C70ES Service Manual ▷ View online
25
AVD-C70ES
• DVD BOARD IC401 CXD3068Q (DIGITAL SIGNAL PROCESSOR, DIGITAL SERVO PROCESSOR)
Pin No.
Pin Name
I/O
Pin Description
1
DVDD0
—
Power supply terminal (+3.3 V) (digital system)
2
XRST
I
Reset signal input from the mechanism controller “L”: reset
3
MUTE
I
Muting on/off control signal input from the mechanism controller “H”: muting on
4
DATA
I
Serial data input from the mechanism controller
5
XLAT
I
Serial data latch pulse signal input from the mechanism controller
6
CLOK
I
Serial data transfer clock signal input from the mechanism controller
7
SENS
O
Internal status (SENSE) signal output to the mechanism controller
8
SCLK
I
SENSE serial data reading clock signal input from the mechanism controller
9
ATSK
I/O
Input/output terminal for anti-shock Not used.
10
WFCK
O
Write frame clock signal output to the DVD decoder
11
RFCK
O
RFCK signal output terminal Not used.
12
XPCK
O
XPCK signal output terminal Not used.
13
GFS
O
Guard frame sync signal output to the mechanism controller
14
C2PO
O
C2 pointer signal output to the DVD decoder
15
SCOR
O
Subcode sync (S0+S1) detection signal output to the DVD decoder and mechanism
controller
16
C4M
O
4.2336 MHz clock signal output terminal Not used.
17
WDCK
O
Guard subcode sync (S0+S1) detection signal output to the DVD decoder
18
DVSS0
—
Ground terminal (digital system)
19
COUT
O
Numbers of track counted signal output to the mechanism controller
20
MIRR
O
Mirror signal output to the mechanism controller
21
DFCT
I/O
Defect signal input/output terminal Not used.
22
FOK
O
Focus OK signal output to the mechanism controller
23
PWMI
I
Spindle motor external control signal input terminal Not used.
24
LOCK
O
GFS is sampled by 460 Hz “H” output when GFS is “H”.
25
MDP
O
Spindle motor servo drive signal output to the DVD decoder
26
SSTP
I
Detection signal input from limit in switch
The optical pick-up is inner position when “H”
27
FSTO
O
2/3 divider output terminal Not used.
28
DVDD1
—
Power supply terminal (+3.3 V) (digital system)
29
SFDR
O
Sled servo drive PWM signal (+) output
30
SRDR
O
Sled servo drive PWM signal (–) output
31
TFDR
O
Tracking servo drive PWM signal (+) output
32
TRDR
O
Tracking servo drive PWM signal (–) output
33
FFDR
O
Focus servo drive PWM signal (+) output
34
FRDR
O
Focus servo drive PWM signal (–) output
35
DVSS1
—
Ground terminal (digital system)
36
TEST
I
Input terminal for the test
37
TES1
I
Input terminal for the test
38
VC
I
Middle point voltage (+1.65 V) input terminal
39
FE
I
Focus error signal input from the DVD/CD RF amplifier
40
SE
I
Sled error signal input from the DVD/CD RF amplifier
41
TE
I
Tracking error signal input from the DVD/CD RF amplifier
42
CE
I
Middle point servo analog signal input
43
RFDC
I
RF signal input from the DVD/CD RF amplifier
44
ADIO
O
Output terminal for the test Not used.
45
AVSS0
—
Ground terminal (analog system)
46
IGEN
I
Stabilized current input for operational amplifiers
26
AVD-C70ES
Pin No.
Pin Name
I/O
Pin Description
47
AVDD0
—
Power supply terminal (+3.3 V) (analog system)
48
ASYO
O
EFM full-swing output terminal
49
ASYI
I
Asymmetry comparator voltage input terminal
50
RFAC
I
EFM signal input from the DVD/CD RF amplifier
51
AVSS1
—
Ground terminal (analog system)
52
CLTV
I
Internal VCO control voltage input terminal
53
FILO
O
Filter output for master PLL
54
FILI
I
Filter input for master PLL
55
PCO
O
Charge pump output for master PLL
56
AVDD1
—
Power supply terminal (+3.3 V) (analog system)
57
BIAS
I
Asymmetry circuit constant current input terminal
58
VCTL
I
VCO control voltage input terminal for the wideband EFM PLL Not used.
59
V16M
O
VCO oscillation output terminal for the wideband EFM PLL Not used.
60
VPCO
O
Charge pump output terminal for the wideband EFM PLL Not used.
61
DVDD2
—
Power supply terminal (+3.3 V) (digital system)
62
ASYE
I
Asymmetry circuit on/off control signal input terminal “L”: off, “H”: on Not used.
63
MD2
I
Digital out on/off control signal input from the mechanism controller
“L”: digital out off, “H”: digital out on
64
DOUT
O
Digital audio signal output to the digital audio interface IC
65
LRCK
O
L/R sampling clock signal (44.1 kHz) output to the DVD decoder
66
PCMD
O
Serial data output to the DVD decoder
67
BCK
O
Bit clock signal (2.8224 MHz) output to the DVD decoder
68
EMPH
O
“L” is output when playback disc is emphasis off
“H” is output when playback disc is emphasis on Not used.
69
XTSL
I
Input terminal for the system clock frequency setting
“L”: 16.9344 MHz, “H”: 33.8688 MHz Fixed at “H” in this set.
70
DVSS2
—
Ground terminal (digital system)
71
XTAI
I
System clock input terminal (33.8688 MHz)
72
XTAO
O
System clock output terminal (33.8688 MHz) Not used.
73
SOUT
O
Serial data output terminal Not used.
74
SOCK
O
Serial data reading clock signal output terminal Not used.
75
XOLT
O
Serial data latch pulse signal output terminal Not used.
76
SQSO
O
Subcode Q data output to the mechanism controller
77
SQCK
I
Subcode Q data reading clock signal input from the mechanism controller
78 SCSY I Input terminal for resynchronism of guard subcode sync (S0+S1) Not used.
79
SBSO
O
Subcode serial data output to the DVD decoder
80
EXCK
I
Subcode serial data reading clock signal input to the DVD decoder
27
AVD-C70ES
• DVD BOARD IC607 CXD9617R (AUDIO DIGITAL SIGNAL PROCESSOR)
Pin No.
Pin Name
I/O
Pin Description
1
VSS
—
Ground terminal
2
XRST
I
Reset signal input from the system controller “L”: reset
3
EXTIN
I
Master clock signal input terminal Not used. (Fixed at “L” in this set.)
4
FS2
I
Sampling frequency selection signal input terminal Not used. (Fixed at “L” in this set.)
5
VDDI
—
Power supply terminal (+2.6 V)
6
FS1
I
Sampling frequency selection signal input terminal Not used. (Fixed at “L” in this set.)
7
PLOCK
O
Internal PLL lock signal output terminal Not used. (Open)
8
VSS
—
Ground terminal
9
MCLK1
I
System clock signal input terminal (13.5 MHz)
10
VDDI
—
Power supply terminal (+2.6 V)
11
VSS
—
Ground terminal
12
MCLK2
O
System clock signal output terminal (13.5 MHz)
13
MS
I
Master/slave selection signal input terminal
“L”: slave, “H”: master (fixed at “L” in this set.)
14
SCKOUT
O
Internal system clock signal output to the D/A converter and stream processor
15
LRCKI1
I
L/R sampling clock signal (44.1 kHz) input from the digital audio processor
16
VDDE
—
Power supply terminal (+3.3 V)
17
BCKI1
I
Bit clock signal (2.8224 MHz) input from the digital audio processor
18
SDI1
I
Front L-ch and R-ch audio serial data input from the digital audio processor
19
LRCKO
O
L/R sampling clock signal (44.1 kHz) output to the D/A converter and stream processor
20
BCKO
O
Bit clock signal (2.8224 MHz) output to the D/A converter and stream processor
21
VSS
—
Ground terminal
22
KFSIO
I
Audio clock signal (11.2896 MHz) input from the digital audio processor
23
SDO1
O
Front L-ch and R-ch audio serial data output to the stream processor
24
SDO2
O
Center and woofer audio serial data output to the stream processor
25
SDO3
O
Rear L-ch and R-ch audio serial data output to the stream processor
26
SDO4
O
Audio serial data output to the D/A converter
27
SPDIF
O
S/PDIF signal output terminal Not used. (Open)
28
LRCKI2
I
L/R sampling clock signal (44.1 kHz) input from the A/D converter
29
BCKI2
I
Bit clock signal (2.8224 MHz) input from the A/D converter
30
SDI2
I
Center and woofer audio serial data input from the digital audio processor
31
VSS
—
Ground terminal
32
HACN
O
Acknowledge signal output to the system controller
33
HDIN
I
Write data input from the system controller
34
HCLK
I
Clock signal input from the system controller
35
HDOUT
O
Read data output to the system controller
36
HCS
I
Chip select signal input from the system controller
37
SDCLK
O
Clock signal output terminal Not used. (Open)
38
CLKEN
O
Clock enable signal output terminal Not used. (Open)
39
RAS
O
Row address strobe signal output terminal Not used. (Open)
40
VDDI
—
Power supply terminal (+2.6 V)
41
VSS
—
Ground terminal
42
CAS
O
Column address strobe signal output terminal Not used. (Open)
43
DQM
O
Output terminal of data input/output mask Not used. (Open)
44
CS0
O
Chip select signal output to the S-RAM
45
WE0
O
Write enable signal output to the S-RAM
28
AVD-C70ES
Pin No.
Pin Name
I/O
Pin Description
46
VDDE
—
Power supply terminal (+3.3 V)
47
WMD1
I
S-RAM wait mode setting terminal Fixed at “H” in this set
48
VSS
—
Ground terminal
49
WMD0
I
S-RAM wait mode setting terminal Fixed at “L” in this set
50
PAGE2
O
Page selection signal output terminal Not used. (Open)
51
VSS
—
Ground terminal
52, 53
PAGE1, PAGE0
O
Page selection signal output terminal Not used. (Open)
54
BOOT
I
Boot mode control signal input terminal Not used. (Fixed at “L” in this set.)
55
BTACT
O
Boot mode state display signal output terminal Not used. (Open)
56
BST
I
Boot trap signal input from the system controller
57
MOD1
I
PLL input frequency selection signal input terminal
“L”: 384fs, “H”: 256fs (fixed at “H” in this set)
58
MOD0
I
Mode setting terminal
“L”: single chip mode, “H”: use prohibition (fixed at “L” in this set)
59
EXLOCK
I
PLL lock error and data error flag input from the digital audio interface IC
60
VDDI
—
Power supply terminal (+2.6 V)
61
VSS
—
Ground terminal
62, 63
A17, A16
O
Address signal output terminal Not used. (Open)
64 to 66
A15 to A13
O
Address signal output to the S-RAM
67
GP10
O
L/R sampling clock signal (44.1 kHz) output to the D/A converter and stream processor
68
GP9
O
Decode signal output to the system controller
69
GP8
I
Bit 1 input terminal of channel status from the digital audio interface IC
70
VDDI
—
Power supply terminal (+2.6 V)
71
VSS
—
Ground terminal
72 to 75
D15 to D12
I/O
Two-way data bus with the S-RAM
76
VDDE
—
Power supply terminal (+3.3 V)
77 to 80
D11 to D8
I/O
Two-way data bus with the S-RAM
81
VSS
—
Ground terminal
82 to 85
A9, A12 to A10
O
Address signal output to the S-RAM
86
TDO
O
Simple emulation data output terminal Not used. (Open)
87
TMS
I
Simple emulation data input start/end detection signal input terminal Not used. (Open)
88
XTRST
I
Simple emulation asychronous break input terminal Not used. (Open)
89
TCK
I
Simple emulation clock signal input terminal Not used. (Open)
90
TDI
I
Simple emulation data input terminal Not used. (Open)
91
VSS
—
Ground terminal
92 to 97
A8 to A3
O
Address signal output to the S-RAM
98, 99
D7, D6
I/O
Two-way data bus with the S-RAM
100
VDDI
—
Power supply terminal (+2.6 V)
101
VSS
—
Ground terminal
102 to 105
D5 to D2
I/O
Two-way data bus with the S-RAM
106
VDDE
—
Power supply terminal (+3.3 V)
107, 108
D1, D0
I/O
Two-way data bus with the S-RAM
109, 110
A2, A1
O
Address signal output to the S-RAM
111
VSS
—
Ground terminal
112
A0
O
Address signal output to the S-RAM
113
PM
I
PLL reset signal input from the system controller “L”: reset
114
SDI3
I
Rear L-ch and R-ch audio serial data input from the digital audio processor
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