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The CCD block is composed of the lens part and CCD part integrated together. One flexible board is connected each for

the CCD part and lens part.

• CCD part

The CCD is driven by the 15V and –7.5V voltages output from the DD board, and converts the input light into the

electrical signal.

Data is output from the CCDOUT terminal according to the horizontal sync clock (H1, H2) and the vertical sync clock

(V1, V2, V3, VSUB) input from the timing generator.

The output of the CCDOUT terminal can be checked on the oscilloscope.

• Lens part

The lens part sets the iris, etc.
The power for the lens block is supplied from the iris control section via the iris flexible board.

Iris open/close operation can be checked visually by increasing or decreasing the brightness of the lens block in the auto

camera mode.

The screen will become totally black when the flexible board of the lens block is cut or the iris remains closed due to the

faulty contact of the connector.

The image data input from the CCD block is sample-held (S/H), and converted to digital signal by the A/D converter.

• S/H, AGC (IC404)

For the analog output signal from the CCD block, the light amount is output as the differential voltage. This differential

voltage is output by sample-holding inside IC404.

The differential voltage is level-adjusted by the AGC (auto gain control) circuit, and output from the DRVOUT terminal

(Pin 8 of IC404).

This output waveform becomes a stepped rectangular wave since it is sample-held.

• A/D converter (IC405)

Sample-held signals are A/D converted by IC405, and the RGB signals of one pixel are each output as 10 bit digital data

(D0 to D9).

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The camera section controls the lens block based on the output signals from the CCD block. During the auto camera mode,

it adjusts the shutter speed according to the image data input from the CCD.

• AE/AWB detector (IC302)

The image signals from the CCD are converted to 10 bit digital data, input to the IC302 to input various detection data.

IC302 detects this digital signal, and outputs serial data for automatic exposure and automatic white balance, etc. to the camera
microprocessor.

• Camera microprocessor (IC301)

The camera microprocessor controls the camera circuit.
The camera microprocessor performs data communication with DSP (IC303), AE/AWB detector (IC302), EVR/DAC

(IC406), TG (IC401), using serial signal terminals (Pins &¶ to &ª).

When performing data communication with each IC, it sets the communication destination using the L active chip select

signal (Pins 5 to 8).

It also performs communication with the SI0/SO0 terminal (Pins $£/$¢) with the main microprocessor every 1/30 seconds,

and at this time, the CS0 terminal (Pin $™) of the chip select becomes “L”. Camera block setting information such as shooting
mode, shutter speed, etc. is transmitted from the main microprocessor by this serial data.

During the auto camera mode, the various detection data input by the CCD are input to the camera microprocessor in serial

data from the AE/AWB detector (IC302). Based on this, the camera iris, shutter speed, CCD image gain, and white balance
values are determined inside the microprocessor, and transmitted in serial data to each IC.

• Electronic control (IC406)

Various control settings are output as a voltage (0 to 5V) by receiving the serial data (DIN Pin !¶) from the camera

microprocessor. The LD terminal (Pin !∞) inputs a load timing pulse signal every 1/30 seconds. (Data is also input every 1/
30.)

• Iris drive amplifier (IC201, IC202)

Iris drive outputs are generated by the iris adjustment voltage set by EVR (IC406) and IRIS_PWM signal from the camera

microprocessor (Pin &¢ of IC301).

IC201 and Q201 are iris drive amplifiers, and IC202 is a feedback loop filter to control the iris drive amplifiers.

• Timing generator (IC401)

The timing generator (TG) outputs the vertical and horizontal timing pulse signals (V1 to V3, H1 to H2) input to the CCD,

and clock (VSUB). V1 to V3 are signals periodically output, and each H1 and H2 are reverse phase clock signals.

The camera block circuit system clock is output from the MCK terminal (Pin $ ¶) by X401 (NTSC:24.54545 MHz,

PAL:24.375 MHz).

• 3.2V regulator (IC402)

Regulates the 3.2V for the TG (IC401) power supply voltage from 5V.

• Vertical drive (IC403)

Voltage-converts the 3.2V timing signal output from TG (IC401) to the –7.5 to 15V timing signals, and outputs to the CCD.

Adjustment Value

Iris offset

Iris gain

CCDOUT offset

CCDOUT gain

Clock frequency

Flash light amount

Terminal

AO1 (Pin !•)

AO2 (Pin !ª)

AO3 (Pin 2)

AO4 (Pin 3), AO5 (Pin 4)

AO10 (Pin 9)

AO11 (Pin !™)

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Converts the digital image data to the analog video data.

• Digital signal processing (IC303)

Converts the input 10-bit digital RGB signals to the luminance signal and color signal. Parameters such as frequency

characteristics, and image color can be varied by setting serial communication from the camera microprocessor.

The Y signal is output in 8-bit signal (DOY0 to DOY7). The C signal is output as alternate B-Y signal and R-Y signal in

the 8-bit signal (DOC0 to DOC7).

During image data output, MWEO (Pin $¶) becomes H, but Q381 turns ON by the H output of the camera microprocessor

(Pin !£ of IC301, WECTL) and performs muting.

But this is currently not used.

• Memory controller:M1 (IC001)

M1 performs data communication with the main microprocessor (IC602), data bus ((D0 to D15), and address line (A1 to

A2) to control the memory data input/output.

During the standby mode, it directly outputs the input image digital signal to the VRAM data line (Pin ^£ of VD0 to Pin $¶

of VD15 of IC002) to rewrite the VRAM data.

Even if the data line for image data is disconnected, image may be displayed. In this case, solarization (image becomes

gradated) may occur.

Check the data line if this occurs.

• VRAM (IC002)

4M bit RAM. Image data from M1 (IC001) is input to VD0 to VD15, and data is rewritten by the write enable signals LWE

(Pin @¢) and HWE (Pin @∞).

The data written is read by M2 (IC101) from the SD0 to SD15 terminal.

• Video encoder, character generator:M2 (IC101)

M2 (IC101) reads the still picture data of VRAM using the DIN0 to DIN15 terminals, and encodes it into the NTSC/PAL

signal. As the signal output is set according to constants such as the circuit resistance, etc., it cannot be switched between
NTSC/PAL.

The M2 also has a character/pattern generator function which displays characters such as a menu screen, adjusting bar, etc.

These display data are written in the VRAM (IC002) by the main microprocessor and read from DIN0 to DIN15 of the M2.

M2 D/A converts digital data inside IC101, and outputs it as analog signal from the YDAO terminal (Pin $§) and CDAO

terminal (Pin #£). It also outputs the sync signal (SYNC) from the VDO terminal (Pin ^™).

It locks X101 clock (NTSC : 14.318 MHz, PAL : 17.734 MHz), and operating clock of the camera block at PLL, amplifies

the output from the phase comparator inside IC101 using the error amplifier (IC102), and adjusts the phase difference.

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Outputs the video signal from the Y/C signal, or displays on the LCD.

• Y signal amplifier (Q202), LPF (FL202)

The SYNC signal and YDAO signal input from CN202 of the video board are mixed by Q202, and the Y signal with the

sync signal is output from the buffer (Q204 emitter).

The amplitude of the Y signal is halved after noise components are eliminated by FL202, and the signal is output to Q206.

• C signal amplifier (Q201), BPF (FL201)

The CDAO signal input from CN202 of the video board is amplified by Q201, and the 3.58 MHz signal is extracted by

FL201.

• Gain control amplifier (IC201)

The amplitude of the Y/C signal input is adjusted according to the CNT-Y and CNT-C signals from the LCD circuit.
The Y signal is input from the IN2 terminal (Pin 7) of IC201, and output at the approximately 1Vp-p amplitude from the

OUT2 terminal (Pin 5).

The C signal is input from the IN1 terminal (Pin 1) of IC201, and output from the OUT1 terminal (Pin 3).

• Output to LCD display

The Y/C signal output from the gain control amplifier (IC201) is resistance-divided, and output from the EVFY and RVFC

terminals to the LCD display.