Sony XR-C7500R / XR-C7500RX Service Manual ▷ View online
33
IC201
LB1930M-TLM
IC250
CXA2510AQ-T4
IC500
BA8270F-E2
1
2
2
3
4
5
6
7
8
9
10
VCC
IN2
S-GND
IN1
NC
NC
OUT2
NC
P-GND
OUT1
CONTROL
CIRCUIT
MOTOR
DRIVE
CIRCUIT
BUFFER
BUFFER
+
–
–
+
–
+
–
+
–
+ –
1
2
3
4
5
6
7
8 9 10
20
19
18
17
16
15
14
13
12
11
21
22
23
26
27
28
29
30
31
32
33
34
37
38
39
40
24
25
PBFB2
PBRIN2
PBREF2
PBFIN2
35
36
PBGND
VCT
PBFIN1
PBREF1
PBRIN1
PBFB1
PBEQ2
PBOUT2
VCC
TAPEIN2
AUXIN2
MSLPF
LINEOUT2
TCH2
NC
PLAY
FF
MSTC
DGND
MSOUT
NC
NRSW
INSW
TAPESW
MSMODE
DRSW
MSSW
NC
TCH1
LINEOUT1
DIREF
AUXIN1
TAPEIN1
PBEQ1
PBOUT1
GND
F2
120
µ
/
70
µ
X1
X1
VCT
+
F1
120
µ
/
70
µ
NR
OFF/B
F3
LPF
VCC
DETECT
MS ON/
OFF
NR
MODE
FWD/RVS
TAPE EQ
TAPE/AUX
NR BIAS
NR
MS
MODE
OFF/B
T2
T1
1
2
3
4
5
5
6
7
8
9
10
14
13
12
11
BUS ON
SWITCH
RESET
SWITCH
BATTERY
SWITCH
BUS ON
RST
BATT
CLK
VREF
DATA
GND
VCC
RST
BUS ON
BUS ON
CLK IN
BU IN
DATA IN
DATA OUT
34
7-16.
IC PIN FUNCTION DESCRIPTION
•
MAIN BOARD IC100 CXD2726Q-4 (DIGITAL SIGNAL PROCESSOR, DIGITAL FILTER, D/A CONVERTER)
Pin No.
Pin Name
I/O
Description
1
VSS1
—
Ground terminal (digital system)
2 to 15
T.P
I
Input terminal for the test (fixed at “L”)
16 to 21
TST0 to TST5
I
Input terminal for the test (fixed at “L”)
22 to 24
JPE1 to JPE3
I
External condition jump terminal “H”: condition jump (fixed at “L”)
25
VDD1
—
Power supply terminal (+3.3V) (digital system)
26
AVS3
—
Ground terminal (for D/A converter 1) (analog system)
27
AOUTL1
O
D/A converter 1 (L-ch side) output terminal
Analog signal output for front side (L-ch side) output in this set
Analog signal output for front side (L-ch side) output in this set
28
AVD3
—
Power supply terminal (+3.3V) (for D/A converter 1) (analog system)
29
AOUTR1
O
D/A converter 1 (R-ch side) output terminal
Analog signal output for rear side (L-ch side) output in this set
Analog signal output for rear side (L-ch side) output in this set
30
AVD5
—
Power supply terminal (+3.3V) (for D/A converter 1) (analog system)
31
AVS5
—
Ground terminal (for D/A converter 1) (analog system)
32
AVD1
—
Power supply terminal (+3.3V) (for L-ch side A/D converter) (analog system)
33
AVS1
—
Ground terminal (for L-ch side A/D converter) (analog system)
34
LREF
O
Connected to the bus control for A/D converter (for L-ch side)
35
LIN
I
A/D converter (L-ch side) analog input terminal
Tuner and bus audio input signal (L-ch side) in this set
Tuner and bus audio input signal (L-ch side) in this set
36
AVS7
—
Ground terminal (for D/A converter 2) (analog system)
37
AVD7
—
Power supply terminal (+3.3V) (for D/A converter 2) (analog system)
38
AOUTL2
O
D/A converter 2 (L-ch side) output terminal Not used (open)
39
AVDX
—
Power supply terminal (+3.3V) (for master clock) (analog system)
40
XTLO38
O
System clock output terminal (16.9344 MHz)
41
XTLI38
I
System clock input terminal (16.9344 MHz)
42
AVSX
—
Ground terminal (for master clock) (analog system)
43
AOUTR2
O
D/A converter 2 (R-ch side) output terminal Not used (open)
44
AVD8
—
Power supply terminal (+3.3V) (for D/A converter 2) (analog system)
45
AVS8
—
Ground terminal (for D/A converter 2) (analog system)
46
RIN
I
A/D converter (R-ch side) analog input terminal
Tuner and bus audio input signal (R-ch side) in this set
Tuner and bus audio input signal (R-ch side) in this set
47
RREF
O
Connected to the bus control for A/D converter (for R-ch side)
48
AVS2
—
Ground terminal (for R-ch side A/D converter) (analog system)
49
AVD2
—
Power supply terminal (+3.3V) (for R-ch side A/D converter) (analog system)
50
AVS6
—
Ground terminal (for D/A converter 3) (analog system)
51
AVD6
—
Power supply terminal (+3.3V) (for D/A converter 3) (analog system)
52
AOUTL3
O
D/A converter 3 (L-ch side) output terminal
Analog signal output for rear side (R-ch side) output in this set
Analog signal output for rear side (R-ch side) output in this set
53
AVD4
—
Power supply terminal (+3.3V) (for D/A converter 3) (analog system)
54
AOUTR3
O
D/A converter 3 (R-ch side) output terminal
Analog signal output for front side (R-ch side) output in this set
Analog signal output for front side (R-ch side) output in this set
55
AVS4
—
Ground terminal (for D/A converter 3) (analog system)
56
VSS2
—
Ground terminal (digital system)
57
XRST
I
System reset signal input from the system controller (IC600) “L”: reset
58
BFOT
O
Master clock signal output terminal Not used (open)
59
SCK
I
Serial data transfer clock signal input from the system controller (IC600) and liquid crystal
display drive controller (IC800)
display drive controller (IC800)
35
Pin No.
Pin Name
I/O
Description
60
REDY
O
Transfer enable signal output to the system controller (IC600)
“L”: transfer prohibition
“L”: transfer prohibition
61
TRDT
O
Serial data output to the system controller (IC600) and liquid crystal display drive controller
(IC800)
(IC800)
62
XLAT
I
Serial data latch pulse input from the system controller (IC600)
63
RVDT
I
Serial data input from the system controller (IC600)
64
XS24
I
Serial data 24/32 bit slot selection signal input terminal
“L”: 24 bit slot, “H”: 32 bit slot (validity at slave mode) (fixed at “H” in this set)
“L”: 24 bit slot, “H”: 32 bit slot (validity at slave mode) (fixed at “H” in this set)
65
VDD2
—
Power supply terminal (+3.3V) (digital system)
66
VSS3
—
Ground terminal (digital system)
67 to 69
SO1 to SO3
O
Serial data output terminal Not used (open)
70
SOUT
O
Serial data output terminal Not used (open)
71 to 73
SI1 to SI3
I
Serial data input terminal Not used (fixed at “L”)
74
SIN
I
Serial data input terminal Not used (fixed at “L”)
75
BCK
I
Bit clock signal (2.8224 MHz) input terminal Not used (fixed at “H”)
76
LRCK
I
L/R sampling clock signal (44.1 kHz) input terminal Not used (fixed at “H”)
77
XMST
I
Bit clock (BCK) and L/R sampling clock (LRCK) signal master/slave mode selection signal input
terminal “L”: master mode, “H”: slave mode (fixed at “L” in this set)
terminal “L”: master mode, “H”: slave mode (fixed at “L” in this set)
78
VDD3
—
Power supply terminal (+3.3V) (digital system)
79
AVSP
—
Ground terminal (PLL system)
80
XPLLEN
I
PLL enable signal input terminal Normally: fixed at “L”
81
PLCLK
O
PLL clock signal output terminal (22.5792 MHz)
82
XECKSTP
I
PLL clock output control signal input terminal Not used (fixed at “L”)
83
AVDP
—
Power supply terminal (+3.3V) (PLL system)
84
VSS4
—
Ground terminal (digital system)
85 to 94
T.P
I
Input terminal for the test Normally: fixed at “L”
95
VDD4
—
Power supply terminal (+3.3V) (digital system)
96
AVSD
—
Ground terminal (for D-RAM)
97 to 99
T.P
I
Input terminal for the test Normally: fixed at “L”
100
AVDD
—
Power supply terminal (+3.3V) (for D-RAM)
36
•
MAIN BOARD IC600 MB90574BPMT-G-265-BND (SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
NC
O
Not used (open)
2
AMSIN
I
Whether a music is present or not from CXA2510AQ (IC250) is detected at auto music sensor
“L”: music is present, “H”: music is not present
“L”: music is present, “H”: music is not present
3
AMSON
O
Tape auto music sensor control signal output to the CXA2510AQ (IC250)
“L” is output to lower the gain for audio level at FF/REW mode
“L” is output to lower the gain for audio level at FF/REW mode
4
SA LAT
O
Serial data latch pulse output for spectrum analyzer section to the liquid crystal display drive
controller (IC800)
controller (IC800)
5
ATT
O
Audio line muting on/off control signal output terminal “H”: muting on
6
SYSRST
O
System reset signal output to the liquid crystal display drive controller (IC800) and SONY bus
interface (IC500) “L”: reset
interface (IC500) “L”: reset
7
F/R
O
Forward/reverse direction control signal output to the CXA2510AQ (IC250)
“L”: reverse direction, “H”: forward direction
“L”: reverse direction, “H”: forward direction
8
VCC
—
Power supply terminal (+5V)
9
TAPE ATT
O
Tape muting on/off control signal output to the CXA2510AQ (IC250) “H”: muting on
Active at ATA, FF/REW mode
Active at ATA, FF/REW mode
10
T. ROM-SDA
I/O
Two-way data bus for tuner EEPROM with the FM/AM tuner unit (TUX1)
11
T. ROM-SCL
I/O
Two-way bus clock signal for tuner EEPROM with the FM/AM tuner unit (TUX1)
12
RX
I
Input terminal at the flash memory data write mode
Front panel open/close detection signal input terminal
“L” is input when the front panel is closed
Front panel open/close detection signal input terminal
“L” is input when the front panel is closed
13
TX
O
Output terminal at the flash memory data write mode
Display serial data output to the liquid crystal display driver (IC901)
Display serial data output to the liquid crystal display driver (IC901)
14
BUS-ON
O
Bus on/off control signal output to the liquid crystal display drive controller (IC800) and SONY
bus interface (IC500) “L”: bus on
bus interface (IC500) “L”: bus on
15
BEEP
O
Beep sound drive signal output terminal
16
NC
O
Not used (open)
17
UNISI
I
Serial data input from the SONY bus interface (IC500)
18
UNISO
O
Serial data output to the SONY bus interface (IC500)
19
UNICKO
O
Serial clock signal output to the liquid crystal display drive controller (IC800) and SONY bus
interface (IC500)
interface (IC500)
20
IF-BW
I
Tuner wide/narrow select signal input terminal “L”: wide, “H”: narrow
Not used (fixed at “L”)
Not used (fixed at “L”)
21
SW SHIFT
O
Not used
22, 23
NC
O
Not used (open)
24
SIRCS
I
Sircs remote control signal input from the remote control receiver (IC951)
25
DSPSI
I
Serial data input from the CXD2726Q (IC100)
26
DSPSO
O
Serial data output to the CXD2726Q (IC100)
27
DSPCKO
O
Serial data transfer clock signal output to the CXD2726Q (IC100) and liquid crystal display drive
controller (IC800)
controller (IC800)
28
DSPPLL
O
PLL clock control signal output terminal Not used (open)
29
DSPMST
O
Bit clock (BCK) and L/R sampling (LRCK) signal master/slave mode selection signal output
terminal “L”: master mode, “H”: slave mode Not used (open)
terminal “L”: master mode, “H”: slave mode Not used (open)
30
NC
O
Not used (open)
31
VOLATT
O
Pre amplifier muting on/off control signal output to the electrical volume (IC10)
“L”: muting on
“L”: muting on
32
TUMUTE
O
Muting on/off control signal output of the FM/AM tuner signal “L”: muting on
33
VSS
—
Ground terminal
34
C
—
Connected to coupling capacitor for the power supply Not used (open)
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