Sony XAV-A1 Service Manual ▷ View online
81
XAV-A1
Pin No.
Pin Name
I/O
Description
137
VSSQ
-
Ground terminal
138
SKIO
O
System clock signal output to the SD-RAMs
139
VCCQ
-
Power supply terminal (+3.3V)
140
TXD0
O
Key data output to the system controller
141
SCKO
O
Not used
142
TXD2
O
Audio data output to the system controller
143
SCPT [3]
O
Not used
144
/RTS2
O
Not used
145
RXD0
I
Key data input from the system controller
146
RXD2
I
Audio data input from the system controller
147
IRQ5
I
Interrupt signal input terminal Not used
148
VSS
-
Ground terminal
149
/RESETM
I
Not used
150
VCC
-
Power supply terminal (+1.9V)
151
IRQ0
I
Interrupt signal input from the graphic controller
152 to 155
IRQ1 to IRQ4
I
Interrupt signal input terminal Not used
156
VSSQ
-
Ground terminal
157
NMI
I
Not used
158
VCCQ
-
Power supply terminal (+3.3V)
159
AUDCK
I
Not used
160, 161
DRQ0, DRQ1
I
Not used
162
ADTRG
I
PAL/NTSC distinction signal input from the LCD interface "L": NTSC, "H": PAL
163, 164
MD0, MD2
I
Clock mode setting terminal Fixed at "L" in this set
165
/RESETP
I
Reset signal input from the system controller "L": reset
166
CA
I
Not used
167
MD3
I
Bus width setting terminal Fixed at "L" in this set
168
MD4
I
Bus width setting terminal Fixed at "H" in this set
169
MD5
I
Endian setting terminal Fixed at "L" in this set
170
AVSS
-
Ground terminal
171 to 174 AN [0] to AN [3]
I
Not used
175
AVCC
-
Power supply terminal (+3.3V)
176
AVSS
-
Ground terminal
82
XAV-A1
MAIN BOARD IC861 HD64413 (GRAPHIC CONTROLLER)
Pin No.
Pin Name
I/O
Description
1, 2
SD4, SD5
I/O
Two-way data bus with the CPU, SD-RAM and flash memory
3
VCC
-
Power supply terminal (+3.3V)
4
SD6
I/O
Two-way data bus with the CPU, SD-RAM and flash memory
5
GND
-
Ground terminal
6 to 11
SD7 to SD12
I/O
Two-way data bus with the CPU, SD-RAM and flash memory
12
VCC
-
Power supply terminal (+3.3V)
13
SD13
I/O
Two-way data bus with the CPU, SD-RAM and flash memory
14
GND
-
Ground terminal
15, 16
SD14, SD15
I/O
Two-way data bus with the CPU, SD-RAM and flash memory
17
GND
-
Ground terminal
18 to 24
SA1 to SA7
I
Address signal input from the CPU
25
VCC
-
Power supply terminal (+3.3V)
26
SA8
I
Address signal input from the CPU
27
GND
-
Ground terminal
28 to 37
SA9 to SA18
I
Address signal input from the CPU
38
VCC
-
Power supply terminal (+3.3V)
39
SA19
I
Address signal input from the CPU
40
GND
-
Ground terminal
41 to 43
SA20 to SA22
I
Address signal input from the CPU
44
/RST 3
I
Reset signal input from the system controller "L": reset
45
MODE0
I
Mode setting terminal Fixed at "H" in this set
46, 47
MODE1, MODE2
I
Mode setting terminal Fixed at "L" in this set
48
CLK0
I
System clock signal input from the clock generator
49
MCLK
O
Clock signal output to the graphic memory
50
PLL VCC
-
Power supply terminal (+3.3V)
51, 52
CAP1, CAP2
-
External capacitor connection terminal
53
PLL GND
-
Ground terminal
54, 55
MD0, MD1
I/O
Two-way data bus with the graphic memory
56
VCC
-
Power supply terminal (+3.3V)
57
MD2
I/O
Two-way data bus with the graphic memory
58
GND
-
Ground terminal
59, 60
MD3, MD4
I/O
Two-way data bus with the graphic memory
61
GND
-
Ground terminal
62, 63
MD5, MD6
I/O
Two-way data bus with the graphic memory
64
VCC
-
Power supply terminal (+3.3V)
65
MD7
I/O
Two-way data bus with the graphic memory
66
GND
-
Ground terminal
67 to 72
MD15 to MD10
I/O
Two-way data bus with the graphic memory
73
VCC
-
Power supply terminal (+3.3V)
74
MD9
I/O
Two-way data bus with the graphic memory
75
GND
-
Ground terminal
76
MD8
I/O
Two-way data bus with the graphic memory
77
/MCS
O
Chip select signal output to the graphic memory
78
/MWE
O
Write enable signal output to the graphic memory
79, 80
LDQM0, LDQM1
O
Write mask signal output to the graphic memory (lower byte)
81
UDQM0
O
Write mask signal output to the graphic memory (upper byte)
83
XAV-A1
Pin No.
Pin Name
I/O
Description
82
VCC
-
Power supply terminal (+3.3V)
83
UDQM1
O
Write mask signal output to the graphic memory (upper byte)
85 to 90
MA12 to MA7
O
Address signal output to the graphic memory
91
VCC
-
Power supply terminal (+3.3V)
92
MA6
O
Address signal output to the graphic memory
93
GND
-
Ground terminal
94, 95
MA5, MA4
O
Address signal output to the graphic memory
96
/MRAS
O
Row address signal output to the graphic memory
97
/MCAS
O
Column address signal output to the graphic memory
98, 99
MA3, MA2
O
Address signal output to the graphic memory
100
VCC
-
Power supply terminal (+3.3V)
101
MA1
O
Address signal output to the graphic memory
102
GND
-
Ground terminal
103
MA0
O
Address signal output to the graphic memory
104 to 108 MD23 to MD19
I/O
Two-way data bus with the graphic memory
109
VCC
-
Power supply terminal (+3.3V)
110
MD18
I/O
Two-way data bus with the graphic memory
111
GND
-
Ground terminal
112, 113
MD17, MD16
I/O
Two-way data bus with the graphic memory
114
MD24
I/O
Two-way data bus with the graphic memory
115
GND
-
Ground terminal
116, 117
MD25, MD26
I/O
Two-way data bus with the graphic memory
118
VCC
-
Power supply terminal (+3.3V)
119
MD27
I/O
Two-way data bus with the graphic memory
120
GND
-
Ground terminal
121 to 124 MD28 to MD31
I/O
Two-way data bus with the graphic memory
125 to 132
VIN0 to VIN7
I
Not used
133
NC
-
Not used
134
/VHS
I
Not used
135
/VVS
I
Not used
136
/VODD
I
Not used
137
VQCLK
I
Not used
138
CLK1
I
System clock signal input terminal
139
VCC
-
Power supply terminal (+3.3V)
140
/HSYNC
O
Horizontal sync signal output terminal
141
GND
-
Ground terminal
142
/VSYNC
O
Vertical sync signal output terminal
143
DAC GND
-
Ground terminal
144
DAC VCC
-
Power supply terminal (+3.3V)
145
Q2R
O
RGB (red) signal output terminal
146
Q2G
O
RGB (green) signal output terminal
147
DAC VCC
-
Power supply terminal (+3.3V)
148
Q2B
O
RGB (blue) signal output terminal
149
DAC GND
-
Ground terminal
150
CBU
O
Not used
151
CBL
O
Not used
152
REXT
O
Not used
84
XAV-A1
Pin No.
Pin Name
I/O
Description
153
DAC VCC
-
Power supply terminal (+3.3V)
154
DAC GND
-
Ground terminal
155
/ODDF
I/O
Not used
156
GND
-
Ground terminal
157
Q2 CSYNC
O
Sync signal output terminal
158
VCC
-
Power supply terminal (+3.3V)
159
DISP
O
Not used
160
GND
-
Ground terminal
161
CDE
O
Data enable signal output terminal
162
/CS Q2UGM
I
Chip select signal input from the CPU
163
/CS Q2REG
I
Chip select signal input from the CPU
164
/RD
I
Read strobe signal input from the CPU
165, 166
/WE0, /WE1
I
Write enable signal input from the CPU
167
/DACK
I
Not used
168
/DREQ
O
Not used
169
/WAIT Q2
O
Hardware wait request signal output to the CPU
170
VCC
-
Power supply terminal (+3.3V)
171
/IRQ Q2
O
Interrupt signal output to the CPU
172
GND
-
Ground terminal
173 to 176
SD0 to SD4
I/O
Two-way data bus with the CPU, SD-RAM and flash memory
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