Sony XAV-A1 Service Manual ▷ View online
77
XAV-A1
Pin No.
Pin Name
I/O
Description
48
MPEG_RST
O
Reset signal output to the MPEG decoder and flash memory "L": reset
49
MPEG_DI
I
Serial data input from the MPEG decoder
50
MPEG_DO
O
Serial data output to the MPEG decoder
51
MPEG_CLK
I
Serial data transfer clock signal input from the MPEG decoder
52
AV5V_ON
O
Power on/off control signal output for AV5V power "H": power on
53
/ZEROR
I
Zero flag (R-ch) input from the D/A converter
54
/ZEROL
I
Zero flag (L-ch) input from the D/A converter
55
NC
O
Not used
56
BEEP
O
Beep sound output terminal
57
DIMMER
O
Dimmer control signal output terminal Not used
58
EXT_PWR
O
Accessory power on/off control signal output terminal for external equipment "H": power on
59
SH_MAIN2
I
Audio data input from the CPU
60
MAIN2_SH
O
Audio data output to the CPU
61
MAIN_SH_5
O
Serial data output to the CPU
62
SH_MAIN_5
I
Serial data input from the CPU
63, 64
AREA3, AREA4
I
Destination setting terminal
65
ACCOFF
O
Accessory off notification signal output to the CPU "L": accessory off
66
RADIO_+B
O
Power on/off control signal output for radio section "H": power on
67
OSC_SW1
O
Oscillation frequency selection signal output terminal for J-bus driver
68
J1850_RES
O
Reset signal output to the J-bus driver "L": reset
69
J1850_AD
O
Address signal output to the J-bus driver
70
J1850_PWR
O
Power on/off control signal output for J-bus driver "H": power on
71
J1850_TXD
I
Serial data input from the J-bus driver
72
J1850_RXD
O
Serial data output to the J-bus driver
73
J1850_SCLK/PAE
O
Serial data transfer clock signal output to the J-bus driver
74
J1850_INT
I
Interrupt signal input from the J-bus driver
75
MPEG_REQ
I
Request signal input from the MPEG decoder
76
DVDEJECT
I
Eject key input terminal
77
LCDDI
O
Serial data output to the LCD driver
78
LCDCL
O
Serial data transfer clock signal output to the LCD driver
79
LCDCE
O
Chip enable signal output to the LCD driver
80
LCDINH
O
Not used
81
OSD_CS
O
Chip select signal output to the OSD driver
82
OSD_SCLK
O
Serial data transfer clock signal output to the OSD driver
83
OSD_CIN
O
Serial data output to the OSD driver
84
PRE_R_MUTE
O
Muting on/off control signal output terminal for rear monitor out (R-ch) "H": muting on
85
PRE_L_MUTE
O
Muting on/off control signal output terminal for rear monitor out (L-ch) "H": muting on
86
NC
O
Not used
87
RCA_R_MUTE
O
Muting on/off control signal output terminal for front and rear (R-ch) "H": muting on
88
RCA_L_MUTE
O
Muting on/off control signal output terminal for front and rear (L-ch) "H": muting on
89
RCA+B
O
Power on/off control signal output for external amplifier "H": power on
90
LCD+B
O
Power on/off control signal output for LCD+14V power "H": power on
91
NC
O
Not used
92
PANT+B
O
Power on/off control signal output for power antenna "H": power on
93, 94
VSW1, VSW2
O
Video selection signal output terminal
95
VMUTE
O
Video muting on/off control signal output terminal
96
AUX2/BC
O
Video selection signal output terminal "L": back camera/TV, "H": AUX2
78
XAV-A1
Pin No.
Pin Name
I/O
Description
97
FAN CONT
O
Fan motor on/off control signal output terminal "H": motor on
98
ILM-ON
O
Key illumination LED and LCD back light LED dimmer control signal output terminal
99
ILMOUT
O
Key illumination LED and LCD back light LED dimmer control signal output terminal
100
NV_OPENNING
I
Initial screnn state detection signal input from the CPU "L": initial screnn state
101
/NV_RST
O
Reset signal output to the CPU and graphic controller "L": reset
102
DVD_EJECT
O
Eject control signal output to the MPEG decoder
103
BVSS
-
Ground terminal
104
BVDD
-
Power supply terminal (+5V)
105, 106
RMSW1, RMSW2
O
Video selection signal output for rear monitor out
107
RMMUTE
O
Muting on/off control signal output terminal for rear monitor out (video)
108
RGB_MUTE
O
Muting on/off control signal output for RGB signal to video amplifier
109
RGB_NAVI
O
OSD selection signal output terminal "H": master mode
110
STBY1
O
Standby signal output to the power amplifier "L": standby
111
LINE OUT MUTE
O
Muting on/off control signal output terminal for front and rear "H": muting on
112
AFMUTE
O
Muting on/off control signal output to the power amplifier "H": muting on
113
LCD_DATA
O
Serial data output to the LCD interface
114
LCD_CLK
O
Serial data transfer clock signal output to the LCD interface
115
LCD_CS
O
Chip select signal output to the LCD interface
116
Q2+B
O
Power on/off control signal output for graphic controller and circuit around it
"H": power on
"H": power on
117
FRQ_CONT2
O
Frequency control signal output for graphic controller and circuit around it to the DC/DC converter
118
ACC_CTL
O
Power on/off control signal output for ACC and +13V power "H": power on
119
ILMIN
I
Illumination line detection signal input terminal
120
PARKIN
I
Parking break detection signal input terminal
121
SL-MOTOR+
O
Slide motor drive signal output terminal
122
SL-MOTOR-
O
Slide motor drive signal output terminal
123
MOTOR_ON
O
Power on/off control signal output for +7V power "H": power on
124
ANGLE0_SW
I
Monitor angle detection switch input terminal
125
PHOTO_SENSOR
I
Motor rotation pulse signal input from the slide motor rotation detection sensor
126
SL-CLOSE_SW
I
Monitor close detection switch input terminal
127
AN-MOTOR+
O
Angle motor drive signal output terminal
128
AN-MOTOR-
O
Angle motor drive signal output terminal
129
ROTARY_SENSOR
I
Motor rotation pulse signal input from the angle motor rotation detection sensor
130
NAVI_OFF
I
Power off permission signal input from the CPU
131
/RVS
I
Reverse detection signal input terminal
132
X_AD
I
X coordinates input from the touch panel (A/D input)
133
Y_AD
I
Y coordinates input from the touch panel (A/D input)
134
VDET
I
Not used
135
TEMP_SENSOR
I
Temperature detection signal input terminal
136
LVCC
I
Power voltage detection terminal 3V or less is abnormal
137
SLVCC
I
Power voltage detection terminal 1.8V or less is abnormal
138
RA_VSM
I
Signal-meter electric field strength detection signal input terminal (AD input)
139
KEY1
I
Key input terminal Not used
140
TEMP_SET
I
Not used
141
KEY3
I
Monitor key input terminal (A/D input)
142
KEY_lCD1
I
Panel key input terminal (A/D input)
143
AM AGC
I
AM AGC detection signal input from the AM/FM tuner (AD input)
144
PANEL_SW
I
Panel attachment detection signal input terminal
79
XAV-A1
MAIN BOARD IC801 HD6417706 (CPU)
Pin No.
Pin Name
I/O
Description
1
VCC_RTC
-
Power supply terminal (+1.9V)
2
XTAL2
O
System clock output terminal for internal real time clock Not used
3
EXTAL2
I
System clock input terminal for internal real time clock Not used
4
VSS_RTC
-
Ground terminal
5 to 10
SD31 to SD26
I/O
Two-way data bus with the SD-RAM
11
VSSQ
-
Ground terminal
12
SD25
I/O
Two-way data bus with the SD-RAM
13
VCCQ
-
Power supply terminal (+3.3V)
14 to 18
SD24 to SD20
I/O
Two-way data bus with the SD-RAM
19
VSS
-
Ground terminal
20
SD19
I/O
Two-way data bus with the SD-RAM
21
VCC
-
Power supply terminal (+1.9V)
22 to 24
SD18 to SD16
I/O
Two-way data bus with the SD-RAM
25
VSSQ
-
Ground terminal
26
SD15
I/O
Two-way data bus with the SD-RAM, flash memory and graphic controller
27
VCCQ
-
Power supply terminal (+3.3V)
28 to 36
SD14 to SD6
I/O
Two-way data bus with the SD-RAM, flash memory and graphic controller
37
VSSQ
-
Ground terminal
38
SD5
I/O
Two-way data bus with the SD-RAM, flash memory and graphic controller
39
VCCQ
-
Power supply terminal (+3.3V)
40 to 44
SD4 to SD0
I/O
Two-way data bus with the SD-RAM, flash memory and graphic controller
45
SA0
O
Address signal output terminal Not used
46
SA1
O
Address signal output to the flash memory and graphic controller
47, 48
SA2, SA3
O
Address signal output to the SD-RAM, flash memory and graphic controller
49
VSSQ
-
Ground terminal
50
SA4
O
Address signal output to the SD-RAM, flash memory and graphic controller
51
VCCQ
-
Power supply terminal (+3.3V)
52 to 60
SA5 to SA13
O
Address signal output to the SD-RAM, flash memory and graphic controller
61
VSSQ
-
Ground terminal
62
SA14
O
Address signal output to the SD-RAM, flash memory and graphic controller
63
VCCQ
-
Power supply terminal (+3.3V)
64
SA15
O
Address signal output to the SD-RAM, flash memory and graphic controller
65 to 70
SA16 to SA21
O
Address signal output to the flash memory and graphic controller
71
VSS
-
Ground terminal
72
SA22
O
Address signal output to the flash memory and graphic controller
73
VCC
-
Power supply terminal (+1.9V)
74 to 76
SA23 to SA25
O
Address signal output terminal Not used
77
/BS
O
Not used
78
/RD
O
Read strobe signal output to the flash memory and graphic controller
79
/WE0
O
Write enable signal output to the SD-RAM, flash memory and graphic controller
80
/WE1
O
Write enable signal output to the SD-RAM and graphic controller
81, 82
/WE2, /WE3
O
Write enable signal output to the SD-RAM
83
RD/WR
O
Read/write selection signal output to the SD-RAMs
84
VSSQ
-
Ground terminal
85
/FCS
O
Chip select signal output to the flash memory
86
VCCQ
-
Power supply terminal (+3.3V)
80
XAV-A1
Pin No.
Pin Name
I/O
Description
87
/CS2
O
Chip select signal output terminal Not used
88
/CS3
O
Chip select signal output to the SD-RAMs
89
/CS Q2UGM
O
Chip select signal output to the graphic controller
90
/CS Q2REG
O
Chip select signal output to the graphic controller
91
/CS6
O
Chip select signal output terminal Not used
92
PANT+B
O
Power on/off control signal output for power antenna "H": power on
93
VSSQ
-
Ground terminal
94
NV BEEP
O
Initial screen state detection signal output to the system controller "L": initial screen state
95
VCCQ
-
Power supply terminal (+3.3V)
96
/RAS
O
Row address signal output to the SD-RAMs
97
PTD [1]
O
Not used
98
/CAS
O
Column address signal output to the SD-RAMs
99
/CASU
O
Not used
100
SEL SYNC
O
Sync selection signal output terminal "L": 10 MHz, "H": 9.6 MHz
101
/IOIS16
I
Not used
102
/BACK
O
Bus acknowledge signal output terminal Not used
103
/BREQ
I
Bus request signal input terminal Not used
104
/WAIT Q2
I
Hardware wait request signal input from the graphic controller
105
CARD_LED
O
Not used
106
ACC OFF
I
Accessory off notification signal input from the system controller "L": accessory off
107
NAVI OFF
I
Power off permission signal input from the system controller
108
FRDY
O
Ready signal output to the flash memory
109 to 112
AUDATA [0] to
AUDATA [3]
I
Not used
113
PTF [4]
I
Not used
114
TDI
I
Not used
115
VSS
-
Ground terminal
116
TCK
I
Not used
117
VCC
-
Power supply terminal (+1.9V)
118
TMS
I
Not used
119
/TRST
I
Not used
120
TDO
I
Not used
121
/ASEBRKAK
I
Not used
122
/ASEMDO
I
Not used
123
VCC_PLL1
-
Power supply terminal (+1.9V)
124
CAP1
-
External capacitor connection terminal
125, 126
VSS_PLL1,
VSS_PLL2
-
Ground terminal
127
CAP2
-
External capacitor connection terminal
128
VCC_PLL2
-
Power supply terminal (+1.9V)
129
MD1
I
Clock mode setting terminal Fixed at "H" in this set
130
VSS
-
Ground terminal
131
XTAL
O
System clock output terminal (14.7456 MHz)
132
EXTAL
I
System clock input terminal (14.7456 MHz)
133, 134
STATUS0,
STATUS1
O
Processor status signal output terminal
135
TCLK
I
Not used
136
PTE [7]
O
Not used
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