Sony XAV-701HD Service Manual ▷ View online
XAV-701HD
57
– MOTOR Board –
IC7002 BA6285AFP-YE2
NC
NC
GND
OUT2
RNF
FIN
VCC
OUT1
5 6
GND
7
17
VM
16
18
POWER SA
VE
19
RIN
20
VREF
21
8 9
CONTROL
TSD
10 – 13
NC
1 – 4
25 – 22
NC
15, 14
– D-SUB7 Board –
IC7301 - 7303 BH7673G-TR
IC903 SN74AVC4T774PWR
IC7304 MM1836A50NRE
A1 3
B1
14
VCCA
16
VCCB
15
DIR1 1
OE
9
A2 4
B2
13
DIR2 2
A3 5
B3
12
DIR3 7
A4 6
B4
11
GND
10
DIR4 8
VIN
4
VGND
5
VOUT 1
GND 2
VCC 3
+
VOUT
4
CONT 1
GND 2
NC 3
VIN
5
+
–
VOLTAGE
REFERENCE
REGULATOR
CURRENT
LIMIT
THERMAL
SHUTDOWN
BIAS
XAV-701HD
58
Pin No.
Pin Name
I/O
Description
1 to 9
MEMDAT2 to
MEMDAT7,
MEMDAT13 to
MEMDAT15
I/O
Two-way data bus with the fl ash memory
10
VDDC
-
Power supply terminal (+1.8V)
11
VDDP
-
Power supply terminal (+3.3V)
12
MEMADD16
O
Address signal output to the fl ash memory
13
MEMCS1
O
Chip select signal output to the fl ash memory
14 to 21
MEMADD15 to
MEMADD8
O
Address signal output to the fl ash memory
22
MEMWR#
O
Write enable signal output to the fl ash memory
23 to 29
MEMADD18,
MEMADD17,
MEMADD17,
MEMADD7 to
MEMADD3
O
Address signal output to the fl ash memory
30
VDDP
-
Power supply terminal (+3.3V)
31 to 33
MEMADD2,
MEMADD1,
MEMADD1,
MEMADD19
O
Address signal output to the fl ash memory
34
USBVBUS
-
USB VBUS terminal Not used
35
USBID
I/O
USB identifi cation signal input/output terminal Not used
36
USBVDDA3P3
-
Power supply terminal (+3.3V)
37
USBDP
I/O
Two-way USB data (positive) bus terminal Not used
38
USBDN
I/O
Two-way USB data (negative) bus terminal Not used
39
USBREF
O
USB reference voltage output terminal Not used
40
USBXO
O
System clock output terminal Not used
41
USBXI
I
System clock input terminal Not used
42
USBVSSPLL
-
Ground terminal
43
USBVDDPLL1V8
-
Power supply terminal (+1.8V)
44 to 46
RAMADD3 to
RAMADD5
O
Address signal output to the SD-RAM
47
VDDIP
-
Power supply terminal (+3.3V)
48 to 51
RAMADD2,
RAMADD6,
RAMADD1,
RAMADD6,
RAMADD1,
RAMADD7
O
Address signal output to the SD-RAM
52
VDDC
I
Power supply terminal (+1.8V)
53 to 55
RAMADD0,
RAMADD8,
RAMADD8,
RAMADD10
O
Address signal output to the SD-RAM
56
VDDP
-
Power supply terminal (+3.3V)
57
GNDC
-
Ground terminal
58, 59
RAMADD9,
RAMADD11
O
Address signal output to the SD-RAM
60
RAMCS0#
O
Chip select signal output to the SD-RAM
61
RAMBA
O
Bank address signal output to the SD-RAM
62
RAMCS1#
O
Chip select signal output to the SD-RAM
63
RAMRAS#
O
Row address signal output to the SD-RAM
64
RAMCAS#
O
Column address signal output to the SD-RAM
65
VDDP
-
Power supply terminal (+3.3V)
66
GNDC
-
Ground terminal
67
RAMWE#
O
Write enable signal output to the SD-RAM
68
RAMDQM
O
Data mask signal output to the SD-RAM
69
GNDPCLK
-
Ground terminal
70
PCLK
O
Clock signal output to the SD-RAM
71
VDDPCLK
-
Power supply terminal (+3.3V)
72 to 75
RAMDAT9 to
RAMDAT6
I/O
Two-way data bus with the SD-RAM
76
VDDP
-
Power supply terminal (+3.3V)
77
GNDC
-
Ground terminal
• IC Pin Function Description
SERVO BOARD IC4 ZR36988HQCG-AN (DVD PROCESSOR)
XAV-701HD
59
Pin No.
Pin Name
I/O
Description
78 to 83
RAMDAT10 to
RAMDAT12,
RAMDAT5 to
RAMDAT5 to
RAMDAT3
I/O
Two-way data bus with the SD-RAM
84
VDDP
-
Power supply terminal (+3.3V)
85
GNDC
-
Ground terminal
86, 87
RAMDAT13,
RAMDAT2
I/O
Two-way data bus with the SD-RAM
88
VDDC
-
Power supply terminal (+1.8V)
89 to 92
RAMDAT14,
RAMDAT1,
RAMDAT15,
RAMDAT2
I/O
Two-way data bus with the SD-RAM
93
VDDP
-
Power supply terminal (+3.3V)
94
CD_DVD#
O
CD/DVD selection signal output to the optical pick-up block “L”: DVD, “H”: CD
95
GNDC
-
Ground terminal
96
DRVSTB
O
Standby signal output to the coil/motor driver
97
SPDIF_OUT
O
S/PDIF signal output terminal Not used
98
ALRCLK
O
L/R sampling clock signal output to the D/A converter and A/D converter
99
ABCLK
O
Bit clock signal output to the D/A converter and A/D converter
100
AMUTE
O
Audio muting on/off control signal output terminal “H”: muting on
101
ML
O
Serial data latch pulse signal output to the D/A converter
102
MC
O
Serial data transfer clock signal output to the D/A converter
103
MD
O
Serial data output to the D/A converter
104
AIN
I
Digital audio signal input from the A/D converter
105
VDDAPWM
-
Power supply terminal (+3.3V)
106
OP_GAIN
O
Gain control signal output to the optical pick-up block
107
CP_DATA_IN
I
Serial data input terminal Not used
108
CP_DATA_OUT
O
Serial data output terminal Not used
109
CP_CLK
O
Serial data transfer clock signal output terminal Not used
110
GNDAPWM
-
Ground terminal
111
HOMESW
I
Limit switch input terminal
112
AOUT2
O
Digital audio signal output to the D/A converter
113
NC
-
Not used
114
AOUT1
O
Digital audio signal output to the D/A converter
115
NC
-
Not used
116
AOUT0
O
Digital audio signal output to the D/A converter
117
GNDC
-
Ground terminal
118
AMCLK
O
Master clock signal output to the D/A converter and A/D converter
119
VDDP
-
Power supply terminal (+3.3V)
120, 121
NC
-
Not used
122
VCLK2
O
Digital video clock signal output terminal Not used
123 to
130
VID7 to VID0
O
Digital video data output terminal Not used
131
FG_IN
I
FG signal input from the coil/motor driver
132, 133
NC
-
Not used
134
IRRCV
-
Not used
135
VDDP
-
Power supply terminal (+3.3V)
136
DUPTD0
O
Main debug UART data output terminal Not used
137
DUPRD0
I
Main debug UART data input terminal Not used
138
DUPTD1
O
Main debug UART data output terminal Not used
139
DUPRD1
I
Main debug UART data input terminal Not used
140
VDDC
-
Power supply terminal (+1.8V)
141
GNDC
-
Ground terminal
142
RESET#
I
Reset signal input from the master controller “L”: reset
143
GNDPLL
-
Ground terminal
144
VDDPLL
-
Power supply terminal (+1.8V)
145
XO
O
System clock signal output terminal (27 MHz)
146
XI
I
System clock signal input terminal (27 MHz)
147
DAC5
O
Analog video signal output terminal Not used
148
GNDDAC_D
-
Ground terminal
XAV-701HD
60
Pin No.
Pin Name
I/O
Description
149
DAC4
O
Analog YUV video signal (Y) output to the panel section
150
VDDDAC
-
Power supply terminal (+3.3V)
151
DAC3
O
Analog composite video signal (CVBS) output to the video processor and REAR OUT jack
152
DAC2
O
Analog YUV video signal (V) output to the panel section
153
VDDDAC
-
Power supply terminal (+3.3V)
154
DAC1
O
Analog YUV video signal (U) output to the panel section
155
RSET
I
Gain adjust signal input terminal Not used
156
GNDDACBS2
-
Ground terminal
157
RFP
I
RF signal (positive) input from the optical pick-up block
158
RFN
I
RF signal (negative) input from the optical pick-up block
159
VDD1AFE
-
Power supply terminal (+3.3V)
160
A
I
A signal input from the optical pick-up block
161
B
I
B signal input from the optical pick-up block
162
VDDAFE
-
Power supply terminal (+3.3V)
163
C
I
C signal input from the optical pick-up block
164
D
I
D signal input from the optical pick-up block
165
J
I
J signal input terminal Not used
166
E
I
E signal input from the optical pick-up block
167
K
I
K signal input terminal Not used
168
F
I
F signal input from the optical pick-up block
169
GNDAFE
-
Ground terminal
170
G
I
G signal input terminal Not used
171
H
I
H signal input terminal Not used
172
GND1AFE
-
Ground terminal
173
VC
O
Reference voltage (+1.65V) output to the optical pick-up block
174
VREF
-
External capacitor connection terminal for internal band-gap voltage generation
175
RESOUT
-
External resistor connection terminal for internal reference voltage generation
176
GNDREF
-
Ground terminal
177
VDDSAFE
-
Power supply terminal (+3.3V)
178
CD_MD
I
Light amount monitor input from the laser diode of optical pick-up block (for CD)
179
DVD_MD
I
Light amount monitor input from the laser diode of optical pick-up block (for DVD)
180
CD_LD
O
Laser diode on/of control signal output terminal (for CD) “H”: laser diode on
181
DVD_LD
O
Laser diode on/of control signal output terminal (for DVD) “H”: laser diode on
182
FOCUS_PWM
O
Focus coil drive signal output terminal
183
VDDPWM
-
Power supply terminal (+3.3V)
184
TRACK_PWM
O
Tracking coil drive signal output terminal
185
GNDPWM
-
Ground terminal
186
SPDL_PWM
O
Spindle motor drive signal output terminal
187, 188
STB, STA
O
Sled motor drive signal output terminal
189
NC
-
Not used
190
VDDC
-
Power supply terminal (+1.8V)
191
GNDC
-
Ground terminal
192
SEN
I
Clear to send signal input from the master controller
193
REQ
O
Request to send signal output to the master controller
194
DUPTD2 for MASTER
O
Serial data output to the master controller
195
DUPRD2 for
MASTER
I
Serial data input from the master controller
196, 197
TP0 for DEBUG,
TP1 for DEBUG
-
Not used
198 to
200
MEMDAT10 to
MEMDAT12
I/O
Two-way data bus with the fl ash memory
201
MEMADD0
O
Address signal output to the fl ash memory
202
MEMCS0#
O
Chip select signal output terminal Not used
203
MEMRD#
O
Read enable signal output to the fl ash memory
204 to
207
MEMDAT0,
MEMDAT8,
MEMDAT1,
MEMDAT8,
MEMDAT1,
MEMDAT9
I/O
Two-way data bus with the fl ash memory
208
VDDC
-
Power supply terminal (+1.8V)
Click on the first or last page to see other XAV-701HD service manuals if exist.