DOWNLOAD Sony WX-800UI Service Manual ↓ Size: 7.44 MB | Pages: 52 in PDF or view online for FREE

Model
WX-800UI
Pages
52
Size
7.44 MB
Type
PDF
Document
Service Manual
Brand
Device
Car Audio
File
wx-800ui.pdf
Date
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WX-800UI
37
Pin No.
Pin Name
I/O
Description
57
MEC_LIMIT
I
Limit in detection switch input terminal
58
Vcc
-
Power supply terminal (+1.18V) (for internal)
59
NC
-
Not used
60
MEC_LOAD
O
Loading motor drive signal (loading direction) output terminal    “H”: motor on
61
Vss
-
Ground terminal
62
PVcc
-
Power supply terminal (+3.3V) (for I/O)
63
XM_Rx
I
Serial data input terminal    Not used
64
DEBUG_Rx
I
Receive data input terminal for the debug    Not used
65
BT_Rx
I
Serial data input terminal    Not used
66
MD_CLKS
I
Fixed at “L” in this unit
67
RTC_X1
I
System clock input terminal (32.768 kHz)
68
RTC_X2
O
System clock output terminal (32.768 kHz)
69
PLLVcc
-
Power supply terminal (+1.18V) (for PLL)
70
EXTAL
I
System clock input terminal (13.333 MHz)
71
XTAL
O
System clock output terminal (13.333 MHz)
72, 73
Vss
-
Ground terminal
74
NMI
I
Fixed at “H” in this unit
75
Vss
-
Ground terminal
76
RES
I
System reset signal input from the reset signal generator and RESET switch    “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it change to “H”
77
PVcc
-
Power supply terminal (+3.3V) (for I/O)
78
NC
-
Not used
79
ILL_IN
I
Illuminate line detection signal input terminal    Not used
80
NC
-
Not used
81
RC_IN0
I
Rotary commander key input terminal
82, 83
KEY_IN0, KEY_IN1
I
Front panel key input terminal
84
RC_IN1
I
Rotary commander shift key input terminal
85
NC
-
Not used
86
AVcc
-
Power supply terminal (+3.3V) (analog system)
87
Vss
-
Ground terminal
88
Avref
-
Reference power supply (+3.3V) terminal (analog system)
89
BSCANP
I
Fixed at “L” in this unit
90
PVcc
-
Power supply terminal (+3.3V) (for I/O)
91
PARADISSO_BCK
I
Audio clock signal input terminal
92
NC
-
Not used
93
Vss
-
Ground terminal
94
SYNC_ON
O
Not used
95
Vcc
-
Power supply terminal (+1.18V) (for internal)
96
XM_PWR
O
Power supply on/off control signal output terminal    Not used
97
TRST
I
Reset signal input terminal for the JTAG    Not used
98
TDO
O
Data output terminal for the JTAG    Not used
99
TDI
I
Data input terminal for the JTAG    Not used
100
TMS
I
Mode selection signal input terminal for the JTAG    Not used
101
TCK
I
Clock signal input terminal for the JTAG    Not used
102
Vss
-
Ground terminal
103
NC
-
Not used
104
EN_SYS
O
Power on/off control signal output to the regulator    “H”: power on
105
Vcc
-
Power supply terminal (+1.18V) (for internal)
106
PWR_ECO
O
Low power mode selection signal output to the regulator    “L”: low power mode
107
Vss
-
Ground terminal
108
USB_OVR
I
USB over current detection signal input from the regulator    “L”: over current
109
PVcc
-
Power supply terminal (+3.3V) (for I/O)
110
USB_ON2
O
USB power on/off control signal output terminal    Not used
111
USB_OVR2
I
USB over current detection signal input terminal    Not used
112
BT_PWR
O
Power on/off control signal output terminal    Not used
113
NC
-
Not used
114
BT_RST
O
Reset signal output terminal    Not used
115
REMOTE1K
O
Rotary commander key control signal output terminal
116
Vss
-
Ground terminal
117
NC
-
Not used
WX-800UI
38
Pin No.
Pin Name
I/O
Description
118
USB_ON
O
USB power on/off control signal output to the regulator    “H”: power on
119
Vcc
-
Power supply terminal (+1.18V) (for internal)
120
NC
-
Not used
121
Vss
-
Ground terminal
122
RE_ON
O
Jog dial pulse pull-up signal output terminal
123
PVcc
-
Power supply terminal (+3.3V) (for I/O)
124
MEC_DSW
I
Chucking end detection switch input terminal    “L”: chucking end detected
125
I2C0_SCL
O
Serial data transfer clock signal output to the electrical volume, regulator and EEPROM
126
I2C0_SDA
I/O
Two-way data bus with the electrical volume, regulator and EEPROM
127
I2C1_SCL
O
Serial data transfer clock signal output to the FM/AM receiver
128
I2C1_SDA
I/O
Two-way data bus with the FM/AM receiver
129, 130
NC
-
Not used
131, 132
RE_IN0, RE_IN1
I
Jog dial pulse input from the rotary encoder
133
BT_TX
O
Serial data output terminal    Not used
134
REMOTE10K
O
Rotary commander key control signal output terminal    Not used
135
DOOR_SW
I
Front panel remove/attach detection signal input terminal    
“L”: front panel is attached    Fixed at “L” in this unit
136
SIRCS
I
Remote control signal input from the remote control receiver
137
MEC_SELFSW
I
Self loading position detection switch input terminal    “L”: self loading position detected
138
Vss
-
Ground terminal
139
USB_X1
I
System clock input terminal (48 MHz)
140
USB_X2
O
System clock output terminal (48 MHz)
141
USBDPVcc
-
Power supply terminal (+3.3V) (for USB digital)
142
USBDPVss
-
Ground terminal (for USB digital)
143 to 
145
NC
-
Not used
146
USBDVcc
-
Power supply terminal (+1.18V) (for USB digital)
147
USBDVss
-
Ground terminal (for USB digital)
148
USBDPVcc
-
Power supply terminal (+3.3V) (for USB digital)
149
USBDPVss
-
Ground terminal (for USB digital)
150
DM0
I/O
Two-way USB data (–) bus with the USB connector
151
DP0
I/O
Two-way USB data (+) bus with the USB connector
152
VBUSIN0
I
VBUS power detection signal input terminal    “H”: VBUS power is detected
153
USBDVcc
-
Power supply terminal (+1.18V) (for USB digital)
154
USBDVss
-
Ground terminal (for USB digital)
155
REFRIN
I
External resistor connection terminal
156
USBAPVss
-
Ground terminal (for USB analog)
157
USBAPVcc
-
Power supply terminal (+3.3V) (for USB analog)
158
USBAVcc
-
Power supply terminal (+1.18V) (for USB analog)
159
USBAVss
-
Ground terminal (for USB analog)
160
USBUVcc
-
Power supply terminal (+1.18V) (for USB 48 MHz)
161
USBUVss
-
Ground terminal (for USB 48 MHz)
162, 163
Vss
-
Ground terminal
164
NC 
(USB_CHG_MOD2)
-
Not used
165
NC (HUB_RST)
-
Not used
166, 167
SF1_D2, SF1_D3
I/O
Two-way serial data with the serial fl ash
168
SF1_CLK
O
Serial data transfer clock signal output to the serial fl ash
169
SF1_CE
O
Chip select signal output to the serial fl ash
170
SF1_D0
I/O
Two-way serial data with the serial fl ash
171
Vss
-
Ground terminal
172
SF1_D1
I/O
Two-way serial data with the serial fl ash
173
USB_CHG_MOD1
O
USB charge control signal output terminal    Not used
174
PVcc
-
Power supply terminal (+3.3V) (for I/O)
175
ATT
O
Audio muting on/off control signal output terminal    “H”: muting on
176
HIT2_RESET
O
Reset signal output terminal    Not used
WX-800UI
39
MAIN  BOARD  IC705  TC94A99FG-003 (SYCH (RF  AMP,  DIGITAL  SERVO  PROCESSOR,  AUDIO  DSP)
Pin No.
Pin Name
I/O
Description
1
LPFO
O
PLL circuit low-pass fi lter amplifi er output terminal
2
PVREF
-
PLL circuit reference voltage (+1.65V) terminal
3
VCOF
O
VCO fi lter terminal
4
RVSS3
-
Ground terminal
5
VCOI
I
DSP VCO control voltage input terminal
6
RVDD3
-
Power supply terminal (+3.3V)
7
SLCO
O
EFM slice level output terminal
8
RFI
I
RF signal input terminal
9
RFRPI
I
RF ripple signal input terminal
10
RFEQO
O
RF equalizer circuit output terminal
11
DCOFC
O
RF equalizer offset compensation low-pass fi lter output terminal
12
AGCI
I
RF signal auto gain control amplifi er input terminal
13
RFO
O
RF signal generation amplifi er output terminal
14
RVSS3
-
Ground terminal
15
FNI2
I
Main beam (B) input from the CD mechanism deck block
16, 17
FNI1, FPI2
I
Main beam (C) input from the CD mechanism deck block
18
FPI1
I
Main beam (A) input from the CD mechanism deck block
19
VDD1_1
-
Power supply terminal (+1.5V)
20
TPI
I
Sub beam (F) input from the CD mechanism deck block
21
TNI
I
Sub beam (E) input from the CD mechanism deck block
22
VRO
O
Reference voltage (+1.65V) output to the CD mechanism deck block
23
AVSS3
-
Ground terminal
24
MDI
I
Laser power detection signal input from the CD mechanism deck block
25
LDO
O
Laser power control signal output to the CD mechanism deck block
26
FSMONIT
O
Not used
27
RFZI
I
RF ripple zero-cross signal input terminal
28
RFRP
O
RF ripple signal output terminal
29
TEI
O
Tracking error signal output terminal
30
AVDD3
-
Power supply terminal (+3.3V)
31
FOO
O
Focus coil control signal output to the CD mechanism deck block
32
TRO
O
Tracking coil control signal output to the CD mechanism deck block
33
VSS_1
-
Ground terminal
34
FMO
O
Sled motor control signal output to the CD mechanism deck block
35
DMO
O
Spindle motor control signal output to the CD mechanism deck block
36
VDDM1
-
Power supply terminal (+1.5V)
37
SRAMSTB
I
Standby signal input from the system controller    “L”: standby
38
VDD1_2
-
Power supply terminal (+1.5V)
39
VDD3_1
-
Power supply terminal (+3.3V)
40, 41
PIO10/CDMON2, 
PIO11/CDMON3
I/O
Not used
42
PIO12
I
Audio data input from the system controller
43
PIO13
I
Bit clock signal input from the pin 49 (PIO19)
44
PIO14
I
L/R sampling clock signal input from the pin 48 (PIO18)
45
PIO15
O
Audio data output to the system controller
46, 47
PIO16, PIO17
I/O
Not used
48
PIO18
O
L/R sampling clock signal output to the system controller
49
PIO19
O
Bit clock signal output to the system controller
50
PIO20
I/O
Not used
51
DVDD12
-
Power supply terminal (+3.3V)
52
DAO1
O
Audio signal (rear R-ch) output to the electrical volume
53
DVSS12
-
Ground terminal
54
DAO2
O
Audio signal (front R-ch) output to the electrical volume
55
DVREF
-
Reference voltage terminal
56
DVDD34
-
Power supply terminal (+3.3V)
57
DAO3
O
Audio signal (front L-ch) output to the electrical volume
58
DVSS34
-
Ground terminal
59
DAO4
O
Audio signal (rear L-ch) output to the electrical volume
60
DVDD5
-
Power supply terminal (+3.3V)
WX-800UI
40
Pin No.
Pin Name
I/O
Description
61
DAO5
O
Audio signal (sub-ch) output to the electrical volume
62
DVSS5
-
Ground terminal
63
VDD1_3
-
Power supply terminal (+1.5V)
64
VSS_2
-
Ground terminal
65
XVSS3
-
Ground terminal
66
XI
I
System clock input terminal (16.9344 MHz)
67
XO
O
System clock output terminal (16.9344 MHz)
68
XVDD3
-
Power supply terminal (+3.3V)
69
ADVDD3
-
Power supply terminal (+3.3V)
70
ADIN1
I
Audio signal (L-ch) input from the electrical volume
71
ADVREFL
O
Reference voltage output terminal
72
ADVCM
O
Reference voltage output terminal
73
ADVREFH
O
Reference voltage output terminal
74
ADIN2
I
Audio signal (R-ch) input from the electrical volume
75
ADVSS3
-
Ground terminal
76
MS
I
Microprocessor interface mode selection signal input terminal    
“L”: serial interface, “H”: parallel interface    Fixed at “L” in this unit
77, 78
BUS0, BUS1
I/O
Serial data input/output terminal    Not used
79
BUS2
O
Serial data output to the system controller
80
BUS3
I
Serial data input from the system controller
81
BUCK
I
Serial data transfer clock signal input from the system controller
82
CCE
I
Chip enable signal input from the system controller
83
VDD3_2
-
Power supply terminal (+3.3V)
84
VSS_3
-
Ground terminal
85
RST
I
Reset signal input from the system controller    “L”: reset
86
VDD1_4
-
Power supply terminal (+1.5V)
87
PIO0
O
Interrupt signal output to the system controller
88
PIO1
O
Request signal output to the system controller
89
PIO2
I
Gate signal input from the system controller
90
PIO3
I
Audio data input from the system controller
91
PIO4
I
Bit clock signal input from the system controller
92
PIO5
I
L/R sampling clock signal input from the system controller
93
PIO6
I
Muting on/off control signal input from the system controller    “L”: muting on
94
PIO7
O
Zero data detection signal output to the system controller
95
PIO8/CDMON0
O
Serial data output to the system controller
96
PIO9/CDMON1
I
Serial data transfer clock signal input from the system controller
97
TEST
I
Test mode setting terminal    Normally fi xed at “L”
98
PDO
O
EFM and PLCK phase difference signal output terminal
99
TMAX
O
TMAX detection result output terminal
100
LPFN
I
PLL circuit low-pass fi lter amplifi er inversion input terminal
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