Sony MEX-DV900 / MEX-DV90EE Service Manual ▷ View online
MEX-DV90EE/DV900
37
IC601 BD9778HFP
IC701 NJM2561F1-TE2
1
VIN
2
SW
6
RT
4
GND
5
INV
7
EN
3
FB
DRIVER
CURRENT
LIMIT
ERROR
AMP
SOFT
START
PWM
COMPARATOR
THERMAL
SHUT DOWN
LATCH
OSC
VREF
1
POWER SAVE
2
VOUT
3
VSAG
6 VCC
5 GND
4 VIN
75 OHM
DRIVER
DRIVER
LOW-PASS
FILTER
CLAMP
MEX-DV90EE/DV900
38
IC802 TDA8588J/N2/R1
MUTING
IN3
12
SVR
VP
10
PGND1
8
VP2
6
SCL
4
SDA
2
IN4
14
PGND3
18
ACGND
16
VP1
20
STB
22
PGND4
24
RST
26
REG1
30
RES-CAP
28
GND
32
REG5
34
BU-CUP
36
OUT3– 3
PGND2/TAB 1
OUT3+ 5
MUTING
OUT1– 7
OUT1+ 9
IN1
REF
11
SGND 13
MUTING
OUT2+ 17
OUT2– 19
IN2 15
MUTING
TEMPERATURE & LOAD
DUMP PROTECTION
AMPLIFIER
TEMPERATURE & LOAD
DUMP PROTECTION
VOLTAGE REGULATOR
PROTECTION/
DIAGNOSTIC
CLIP DETECT/
DIAGNOSTIC
ENABLE
LOGIC
STANDBY/
MUTING
IIC-BUS
INTERFACE
OUT4+ 21
OUT4– 23
DIAG 25
SW2
(REGULATOR & SWITCH BLOCK)
27
SW1 29
REG3 31
REG4 33
VP 35
REG2 37
RESET
REGULATOR 1
REGULATOR 3
REGULATOR 4
REGULATOR 2
REGULATOR 5
MEX-DV90EE/DV900
39
– KEY Board –
IC901 LC75826WH-US-E
48 S48
47 S47
46 S46
45 S45
44 S44
43 S43
42 S42
41 S41
40 S40
39 S39
47 S47
46 S46
45 S45
44 S44
43 S43
42 S42
41 S41
40 S40
39 S39
19
S19
20
S20
17
S17
18
S18
21
S21
22
S22
23
S23
24
S24
25
S25
26
S26
27
S27
28
S28
3
P3/S3
4
P4/S4
1
P1/S1
2
P2/S2
5
P5/S5
6
P6/S6
7
P7/S7
8
P8/S8
9
S9
10
S10
11
S11
12
S12
52
COM3
51
COM4
59
VSS
58
VDD2
57
VDD1
56
VDD
64
DI
63
CL
62
CE
60
S52/OSCI
55
S51
61
INH
COMMON
DRIVER
CLOCK
GENERATOR
CCB INTERFACE
SHIFT REGISTER
CONTROL
REGISTER
SEGMENT DRIVER & LATCH
13
S13
14
S14
15
S15
16
S16
29
S29
30
S30
31
S31
32
S32
38 S38
37 S37
36 S36
35 S35
34 S34
33 S33
37 S37
36 S36
35 S35
34 S34
33 S33
50
S50
49
S49
54
COM1
53
COM2
MEX-DV90EE/DV900
40
• IC Pin Function Description
SERVO BOARD IC4 ZR36886HLCG-A (DVD PROCESSOR)
SERVO BOARD IC4 ZR36886HLCG-A (DVD PROCESSOR)
Pin No.
Pin Name
I/O
Description
1 to 7
NOT USED
O
Not used
8
SSCCLK
I
Serial data transfer clock signal input terminal Not used
9
SSCTXD
O
Serial data output terminal Not used
10
SSCRXD
I
Serial data input terminal Not used
11
MEMCS1#
O
Chip enable signal output terminal Not used
12
VDDP
-
Power supply terminal (+3.3V)
13 to 17
MEMADD15,
MEMADD16,
MEMADD16,
MEMADD14 to
MEMADD12
O
Address signal output to the fl ash memory
18
MEMDAT15
I/O
Two-way data bus with the fl ash memory
19
MEMADD11
O
Address signal output to the fl ash memory
20
MEMDAT7
I/O
Two-way data bus with the fl ash memory
21
GNDP
-
Ground terminal
22
MEMADD10
O
Address signal output to the fl ash memory
23
MEMDAT14
I/O
Two-way data bus with the fl ash memory
24
MEMADD9
O
Address signal output to the fl ash memory
25
MEMDAT6
I/O
Two-way data bus with the fl ash memory
26
MEMADD8
O
Address signal output to the fl ash memory
27, 28
MEMDAT13,
MEMDAT5
I/O
Two-way data bus with the fl ash memory
29
MEMADD20
O
Address signal output to the fl ash memory
30
VDDP
-
Power supply terminal (+3.3V)
31
MEMDAT12
I/O
Two-way data bus with the fl ash memory
32
MEMWR#
O
Write enable signal output to the fl ash memory
33
MEMDAT4
I/O
Two-way data bus with the fl ash memory
34
VDDC
-
Power supply terminal (+1.8V)
35, 36
MEMDAT11,
MEMDAT3
I/O
Two-way data bus with the fl ash memory
37
MEMADD19
O
Address signal output to the fl ash memory
38
GNDC
-
Ground terminal
39
MEMDAT10
I/O
Two-way data bus with the fl ash memory
40
MEMADD18
O
Address signal output to the fl ash memory
41
GNDP
-
Ground terminal
42
MEMDAT2
I/O
Two-way data bus with the fl ash memory
43
MEMADD17
O
Address signal output to the fl ash memory
44
MEMDAT9
I/O
Two-way data bus with the fl ash memory
45
MEMADD7
O
Address signal output to the fl ash memory
46
MEMDAT1
I/O
Two-way data bus with the fl ash memory
47
MEMADD6
O
Address signal output to the fl ash memory
48
MEMDAT8
I/O
Two-way data bus with the fl ash memory
49
MEMADD5
O
Address signal output to the fl ash memory
50
VDDP
-
Power supply terminal (+3.3V)
51
MEMDAT0
I/O
Two-way data bus with the fl ash memory
52
MEMADD4
O
Address signal output to the fl ash memory
53
MEMRD#
O
Output enable signal output to the fl ash memory
54, 55
MEMADD3,
MEMADD2
O
Address signal output to the fl ash memory
56
MEMCS0#
O
Chip enable signal output to the fl ash memory
57, 58
MEMADD1,
MEMADD0
O
Address signal output to the fl ash memory
59
GNDP
-
Ground terminal
60, 61
VDD, VDDP
-
Power supply terminal (+3.3V)
62, 63
NOT USED
O
Not used
64
RAMCKE
O
Clock enable signal output to the SD-RAM
65
VDD
-
Power supply terminal (+3.3V)
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