Sony MEX-DV700 / MEX-DV707 Service Manual ▷ View online
MEX-DV700/DV707
33
IC801 TDA8588AJ/N2/R1
MUTING
IN3
12
SVR
VP
10
PGND1
8
VP2
6
SCL
4
SDA
2
IN4
14
PGND3
18
ACGND
16
VP1
20
STB
22
PGND4
24
RST
26
REG1
30
RES-CAP
28
GND
32
REG5
34
BU-CUP
36
OUT3– 3
PGND2/TAB 1
OUT3+ 5
MUTING
OUT1– 7
OUT1+ 9
IN1
REF
11
SGND 13
MUTING
OUT2+ 17
OUT2– 19
IN2 15
MUTING
TEMPERATURE & LOAD
DUMP PROTECTION
AMPLIFIER
TEMPERATURE & LOAD
DUMP PROTECTION
VOLTAGE REGULATOR
PROTECTION/
DIAGNOSTIC
CLIP DETECT/
DIAGNOSTIC
ENABLE
LOGIC
STANDBY/
MUTING
IIC-BUS
INTERFACE
OUT4+ 21
OUT4– 23
DIAG 25
SW2
(REGULATOR & SWITCH BLOCK)
27
SW1 29
REG3 31
REG4 33
VP 35
REG2 37
RESET
REGULATOR 1
REGULATOR 3
REGULATOR 4
REGULATOR 2
REGULATOR 5
IC803 TK11133CSCL-G
CONTROL
CIRCUIT
BANDGAP
REFERENCE
+
–
OVER HEAT &
OVER CURRENT
PROTECTION
1
VCONT
3
NP
2
GND
4
VOUT
5
VIN
MEX-DV700/DV707
34
– KEY Board –
IC901 LC75829PWH-US-H
48 S48
47 S47
46 S46
45 S45
44 S44
43 S43
42 S42
41 S41
40 S40
39 S39
47 S47
46 S46
45 S45
44 S44
43 S43
42 S42
41 S41
40 S40
39 S39
19
S19
20
S20
17
S17
18
S18
21
S21
22
S22
23
S23
24
S24
25
S25
26
S26
27
S27
28
S28
3
P3/S3
4
P4/S4
1
P1/S1
2
P2/S2
5
S5
6
S6
7
S7
8
S8
9
S9
10
S10
11
S11
12
S12
52
COM3
51
S51/COM4
59
VSS
58
VDD2
57
VDD1
56
VDD
64
DI
63
CL
62
CE
60
S53/OSCI
55
S52
61
INH
COMMON
DRIVER
CLOCK
GENERATOR
CCB INTERFACE
SHIFT REGISTER
CONTROL
REGISTER
SEGMENT DRIVER & LATCH
13
S13
14
S14
15
S15
16
S16
29
S29
30
S30
31
S31
32
S32
38 S38
37 S37
36 S36
35 S35
34 S34
33 S33
37 S37
36 S36
35 S35
34 S34
33 S33
50
S50
49
S49
54
COM1
53
COM2
MEX-DV700/DV707
35
• IC Pin Function Description
SERVO BOARD IC4 ZR36988HQCG-A (DVD PROCESSOR)
Pin No.
Pin Name
I/O
Description
1 to 9
MEMDAT2 to
MEMDAT7,
MEMDAT13 to
MEMDAT15
I/O
Two-way data bus with the fl ash memory
10
VDDC
I
Power supply terminal (+1.8V)
11
VDDP
-
Power supply terminal (+3.3V)
12
MEMADD16
O
Address signal output to the fl ash memory
13
MEMCS1
O
Chip select signal output to the fl ash memory
14 to 21
MEMADD15 to
MEMADD8
O
Address signal output to the fl ash memory
22
MEMWR#
O
Write enable signal output to the fl ash memory
23 to 29
MEMADD18,
MEMADD17,
MEMADD17,
MEMADD7 to
MEMADD3
O
Address signal output to the fl ash memory
30
VDDP
-
Power supply terminal (+3.3V)
31 to 33
MEMADD2,
MEMADD1,
MEMADD1,
MEMADD19
O
Address signal output to the fl ash memory
34
USBVBUS
-
USB VBUS terminal Not used
35
USBID
I/O
USB identifi cation signal input/output terminal Not used
36
USBVDDA3P3
-
Power supply terminal (+3.3V)
37
USBDP
I/O
Two-way USB data (positive) terminal Not used
38
USBDN
I/O
Two-way USB data (negative) terminal Not used
39
USBREF
O
USB reference voltage output terminal Not used
40
USBXO
O
System clock output terminal (for USB) Not used
41
USBXI
I
System clock input terminal (for USB) Not used
42
USBVSSPLL
-
Ground terminal
43
USBVDDPLL1V8
-
Power supply terminal (+1.8V)
44 to 46
RAMADD3 to
RAMADD5
O
Address signal output to the SD-RAM
47
VDDIP
-
Power supply terminal (+3.3V)
48 to 51
RAMADD2, RAMADD6,
RAMADD1, RAMADD7
O
Address signal output to the SD-RAM
52
VDDC
I
Power supply terminal (+1.8V)
53 to 55
RAMADD0, RAMADD8,
RAMADD10
O
Address signal output to the SD-RAM
56
VDDP
-
Power supply terminal (+3.3V)
57
GNDC
-
Ground terminal
58, 59
RAMADD9,
RAMADD11
O
Address signal output to the SD-RAM
60
RAMCS0#
O
Chip select signal output to the SD-RAM
61
RAMBA
O
Bank address signal output to the SD-RAM
62
RAMCS1#
O
Chip select signal output to the SD-RAM
63
RAMRAS#
O
Row address signal output to the SD-RAM
64
RAMCAS#
O
Column address signal output to the SD-RAM
65
VDDP
-
Power supply terminal (+3.3V)
66
GNDC
-
Ground terminal
67
RAMWE#
O
Write enable signal output to the SD-RAM
68
RAMDQM
O
Data mask signal output to the SD-RAM
69
GNDPCLK
-
Ground terminal
70
PCLK
O
Clock signal output to the SD-RAM
71
VDDPCLK
-
Power supply terminal (+3.3V)
72 to 75
RAMDAT9 to
RAMDAT6
I/O
Two-way data bus with the SD-RAM
76
VDDP
-
Power supply terminal (+3.3V)
77
GNDC
-
Ground terminal
MEX-DV700/DV707
36
Pin No.
Pin Name
I/O
Description
78 to 83
RAMDAT10 to
RAMDAT12, RAMDAT5
to RAMDAT3
I/O
Two-way data bus with the SD-RAM
84
VDDP
-
Power supply terminal (+3.3V)
85
GNDC
-
Ground terminal
86, 87
RAMDAT13, RAMDAT2
I/O
Two-way data bus with the SD-RAM
88
VDDC
-
Power supply terminal (+1.8V)
89 to 92
RAMDAT14,
RAMDAT1,
RAMDAT15, RAMDAT2
I/O
Two-way data bus with the SD-RAM
93
VDDP
-
Power supply terminal (+3.3V)
94
CD_DVD#
O
CD/DVD selection signal output to the optical pick-up block “L”: DVD, “H”: CD
95
GNDC
-
Ground terminal
96
DRVSTB
O
Standby signal output to the coil/motor driver
97
SPDIF_OUT
O
S/PDIF signal output terminal Not used
98
ALRCLK
O
L/R sampling clock signal output to the D/A converter and D/A converter
99
ABCLK
O
Bit clock signal output to the D/A converter and D/A converter
100
AMUTE
O
Analog muting on/off control signal output terminal “H”: muting on
101
ML
O
Serial data latch pulse signal output to the D/A converter
102
MC
O
Serial data transfer clock signal output to the D/A converter
103
MD
O
Serial data output to the D/A converter
104
AIN
I
Digital audio data input from the A/D converter
105
VDDAPWM
-
Power supply terminal (+3.3V)
106
OP_GAIN
O
Gain control signal output to the optical pick-up block
107
CP_DATA_IN
I
Serial data input terminal Not used
108
CP_DATA_OUT
O
Serial data output terminal Not used
109
CP_CLK
O
Serial data transfer clock signal output terminal Not used
110
GNDAPWM
-
Ground terminal
111
HOMESW
I
Limit switch input terminal
112
AOUT2
O
Digital audio data output to the D/A converter
113
NC
-
Not used
114
AOUT1
O
Digital audio data output to the D/A converter
115
NC
-
Not used
116
AOUT0
O
Digital audio data output to the D/A converter
117
GNDC
-
Ground terminal
118
AMCLK
O
Master clock signal output to the D/A converter and D/A converter
119
VDDP
-
Power supply terminal (+3.3V)
120, 121
NC
-
Not used
122
VCLK2
O
Digital video clock signal output terminal Not used
123 to 130
VID7 to VID0
O
Digital video data output terminal Not used
131
FG_IN
I
FG signal input from the coil/motor driver
132, 133
NC
-
Not used
134
IRRCV
-
Not used
135
VDDP
-
Power supply terminal (+3.3V)
136
DUPTD0
O
Main debug UART data output terminal Not used
137
DUPRD0
I
Main debug UART data input terminal Not used
138
DUPTD1
O
Main debug UART data output terminal Not used
139
DUPRD1
I
Main debug UART data input terminal Not used
140
VDDC
-
Power supply terminal (+1.8V)
141
GNDC
-
Ground terminal
142
RESET#
I
Reset signal input from the system controller “L”: reset
143
GNDPLL
-
Ground terminal
144
VDDPLL
-
Power supply terminal (+1.8V)
145
XO
O
System clock signal output terminal (27 MHz)
146
XI
I
System clock signal input terminal (27 MHz)
147
DAC5
O
Analog video data output terminal Not used
148
GNDDAC_D
-
Ground terminal
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