Sony MEX-DV1000 / MEX-DV2000 Service Manual ▷ View online
45
MEX-DV1000/DV2000
IC802 TDA8588AJ/N2/R1
MUTING
IN3
12
SVR
VP
10
PGND1
8
VP2
6
SCL
4
SDA
2
IN4
14
PGND3
18
ACGND
16
VP1
20
STB
22
PGND4
24
RST
26
REG1
30
RES-CAP
28
GND
32
REG5
34
BU-CUP
36
OUT3– 3
PGND2/TAB 1
OUT3+ 5
MUTING
OUT1– 7
OUT1+ 9
IN1
REF
11
SGND 13
MUTING
OUT2+ 17
OUT2– 19
IN2 15
MUTING
TEMPERATURE & LOAD
DUMP PROTECTION
AMPLIFIER
TEMPERATURE & LOAD
DUMP PROTECTION
VOLTAGE REGULATOR
PROTECTION/
DIAGNOSTIC
CLIP DETECT/
DIAGNOSTIC
ENABLE
LOGIC
STANDBY/
MUTING
IIC-BUS
INTERFACE
OUT4+ 21
OUT4– 23
DIAG 25
SW2
(REGULATOR & SWITCH BLOCK)
27
SW1 29
REG3 31
REG4 33
VP 35
REG2 37
RESET
REGULATOR 1
REGULATOR 3
REGULATOR 4
REGULATOR 2
REGULATOR 5
IC803 BD9300FV-FE2
1
DTC
2
RT
3
CT
5
OUT
6
N.C.
7
GND
4
FB
14 NON
13 1/2VREF
12 INV
11 VREF
10 CTL
9
SCP
8
VCC
OSC
VREF
TIMER
LATCH
LATCH
+
–
–
+
–
46
MEX-DV1000/DV2000
•
IC Pin Function Description
SERVO BOARD IC4 ZR36886HLCG-SA (DVD PROCESSOR)
Pin No.
Pin Name
I/O
Description
1 to 7
NOT USED
O
Not used
8
SSCCLK
I
Serial data transfer clock signal input terminal Not used
9
SSCTXD
O
Serial data output terminal Not used
10
SSCRXD
I
Serial data input terminal Not used
11
MEMCS1#
O
Chip enable signal output to the flash memory
12
VDDP
-
Power supply terminal (+3.3V)
13 to 17
MEMADD15,
MEMADD16,
MEMADD16,
MEMADD14 to
MEMADD12
O
Address signal output to the flash memory
18
MEMDAT15
I/O
Two-way data bus with the flash memory
19
MEMADD11
O
Address signal output to the flash memory
20
MEMDAT7
I/O
Two-way data bus with the flash memory
21
GNDP
-
Ground terminal
22
MEMADD10
O
Address signal output to the flash memory
23
MEMDAT14
I/O
Two-way data bus with the flash memory
24
MEMADD9
O
Address signal output to the flash memory
25
MEMDAT6
I/O
Two-way data bus with the flash memory
26
MEMADD8
O
Address signal output to the flash memory
27, 28
MEMDAT13,
MEMDAT5
I/O
Two-way data bus with the flash memory
29
MEMADD20
O
Address signal output to the flash memory
30
VDDP
-
Power supply terminal (+3.3V)
31
MEMDAT12
I/O
Two-way data bus with the flash memory
32
MEMWR#
O
Write enable signal output to the flash memory
33
MEMDAT4
I/O
Two-way data bus with the flash memory
34
VDDC
-
Power supply terminal (+1.8V)
35, 36
MEMDAT11,
MEMDAT3
I/O
Two-way data bus with the flash memory
37
MEMADD19
O
Address signal output to the flash memory
38
GNDC
-
Ground terminal
39
MEMDAT10
I/O
Two-way data bus with the flash memory
40
MEMADD18
O
Address signal output to the flash memory
41
GNDP
-
Ground terminal
42
MEMDAT2
I/O
Two-way data bus with the flash memory
43
MEMADD17
O
Address signal output to the flash memory
44
MEMDAT9
I/O
Two-way data bus with the flash memory
45
MEMADD7
O
Address signal output to the flash memory
46
MEMDAT1
I/O
Two-way data bus with the flash memory
47
MEMADD6
O
Address signal output to the flash memory
48
MEMDAT8
I/O
Two-way data bus with the flash memory
49
MEMADD5
O
Address signal output to the flash memory
50
VDDP
-
Power supply terminal (+3.3V)
51
MEMDAT0
I/O
Two-way data bus with the flash memory
52
MEMADD4
O
Address signal output to the flash memory
53
MEMRD#
O
Output enable signal output to the flash memory
47
MEX-DV1000/DV2000
Pin No.
Pin Name
I/O
Description
54, 55
MEMADD3,
MEMADD2
O
Address signal output to the flash memory
56
MEMCS0#
O
Chip enable signal output to the flash memory
57, 58
MEMADD1,
MEMADD0
O
Address signal output to the flash memory
59
GNDP
-
Ground terminal
60, 61
VDD, VDDP
-
Power supply terminal (+3.3V)
62, 63
NOT USED
O
Not used
64
RAMCKE
O
Clock enable signal output to the SD-RAM
65
VDD
-
Power supply terminal (+3.3V)
66, 67
NOT USED
O
Not used
68
GND
-
Ground terminal
69 to 73
RAMADD4,
RAMADD3,
RAMADD5,
RAMADD2,
RAMADD3,
RAMADD5,
RAMADD2,
RAMADD6
O
Address signal output to the SD-RAM
74
VDDP
-
Power supply terminal (+3.3V)
75 to 77
RAMADD1,
RAMADD7,
RAMADD7,
RAMADD0
O
Address signal output to the SD-RAM
78
GNDP
-
Ground terminal
79
RAMADD8
O
Address signal output to the SD-RAM
80
VDDC
-
Power supply terminal (+1.8V)
81
RAMADD10
O
Address signal output to the SD-RAM
82
GNDC
-
Ground terminal
83
RAMADD9
O
Address signal output to the SD-RAM
84
VDDP
-
Power supply terminal (+3.3V)
85
RAMADD11
O
Address signal output to the SD-RAM
86, 87
RAMCS0,
RAMBA0
O
Bank address signal output to the SD-RAM
88
GNDP
-
Ground terminal
89
RAMCS1
O
Chip select signal output to the SD-RAM
90
RAMRAS#
O
Row address signal output to the SD-RAM
91
RAMCAS#
O
Column address signal output to the SD-RAM
92
VDDP
-
Power supply terminal (+3.3V)
93
RAMWE#
O
Write enable signal output to the SD-RAM
94
RAMDQM
O
Write mask signal output to the SD-RAM
95
GNDPCLK
-
Ground terminal
96
PCLK
O
Clock signal output to the SD-RAM
97
VDDPCLK
-
Power supply terminal (+3.3V)
98
RAMDAT8
I/O
Two-way data bus with the SD-RAM
99
GNDP
-
Ground terminal
100 to 102
RAMDAT7,
RAMDAT9,
RAMDAT9,
RAMDAT6
I/O
Two-way data bus with the SD-RAM
103
VDDP
-
Power supply terminal (+3.3V)
48
MEX-DV1000/DV2000
Pin No.
Pin Name
I/O
Description
104 to 106
RAMDAT10,
RAMDAT5,
RAMDAT11
I/O
Two-way data bus with the SD-RAM
107
GNDP
-
Ground terminal
108
RAMDAT4
I/O
Two-way data bus with the SD-RAM
109
VDDC
-
Power supply terminal (+1.8V)
110
RAMDAT12
I/O
Two-way data bus with the SD-RAM
111
GNDC
-
Ground terminal
112
RAMDAT3
I/O
Two-way data bus with the SD-RAM
113
VDDP
-
Power supply terminal (+3.3V)
114 to 116
RAMDAT13,
RAMDAT2,
RAMDAT14
I/O
Two-way data bus with the SD-RAM
117
GNDP
-
Ground terminal
118 to 120
RAMDAT1,
RAMDAT15,
RAMDAT0
I/O
Two-way data bus with the SD-RAM
121
VDDP
-
Power supply terminal (+3.3V)
122
NOT USED
O
Not used
123
GNDP
-
Ground terminal
124
ICGPCIO0
O
Serial data transfer clock signal output to the D/A converter
125
IDGPCIO0
O
Serial data output to the D/A converter
126
NOT USED
O
Not used
127 to 129 AOUT2 to AOUT0
O
Audio data output to the D/A converter
130
AIN2
O
Chip select signal output to the D/A converter
131
ALRCLK
O
L/R sampling clock signal output to the D/A converter and A/D converter
132
ABCLK
O
Bit clock signal output to the D/A converter and A/D converter
133
GNDPA2
-
Ground terminal
134
AMCLK
O
Master clock signal output to the D/A converter and A/D converter
135
VDDPA2
-
Power supply terminal (+3.3V)
136
AIN1
I
Audio data input from the A/D converter
137
HOME
I
Limit switch input terminal
138
AMUTE
O
Analog muting on/off control signal output to the system controller and muting circuit
"H": muting on
"H": muting on
139
GNDP
-
Ground terminal
140
VCLK
O
Digital video clock signal output terminal Not used
141
VDDP
-
Power supply terminal (+3.3V)
142 to 145
VID7 to VID4
O
Digital video data output terminal Not used
146
GNDC
-
Ground terminal
147
VDDC
-
Power supply terminal (+1.8V)
148 to 151
VID3 to VID0
O
Digital video data output terminal Not used
152, 153
NOT USED
O
Not used
154
VDDP
-
Power supply terminal (+3.3V)
155, 156
GNDP, GNDPLL
-
Ground terminal
157
RESET#
I
Reset signal input from the system controller "L": reset
158
VDDPLL
-
Power supply terminal (+1.8V)
159
XO
O
System clock output terminal (27 MHz)
160
XIN
I
System clock input terminal (27 MHz)
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