DOWNLOAD Sony MEX-1HD Service Manual ↓ Size: 7.32 MB | Pages: 124 in PDF or view online for FREE

Model
MEX-1HD
Pages
124
Size
7.32 MB
Type
PDF
Document
Service Manual
Brand
Device
Car Audio
File
mex-1hd.pdf
Date
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89
MEX-1HD
Pin No.
Pin Name
I/O
Description
111
TKTINT
O
Not used
112
MD0
I
Mode setting terminal    Fixed at “H” in this set
113
VDE7
—
Power supply terminal (+3.3V)
114
MD1
I
Mode setting terminal    Fixed at “L” in this set
115
MD2
I
Mode setting terminal    Fixed at “H” in this set
116
TRST
I
Not used
117
VSS13
—
Ground terminal
118
CLKOUT
O
System clock signal output terminal    Not used
119
CLKSEL0
I
Clock mode setting terminal    Fixed at “H” in this set
120
CLKSEL1
I
Clock mode setting terminal    Fixed at “H” in this set
90
MEX-1HD
•
 MAIN BOARD  IC4301 ISP1161BD-118 (USB INTERFACE)
Pin No.
Pin Name
I/O
Description
1
D_GND
—
Ground terminal (for digital system)
2 to 7
D2 to D7
I/O
Two-way data bus with the CPU, CPU/ATA interface IC, memory stick interface IC,
display controller, 64MB flash memory and 128MB SD-RAM
8
D_GND
—
Ground terminal (for digital system)
9 to 14
D8 to D13
I/O
Two-way data bus with the CPU, CPU/ATA interface IC, memory stick interface IC,
display controller, 64MB flash memory and 128MB SD-RAM
15
D_GND
—
Ground terminal (for digital system)
16, 17
D14, D15
I/O
Two-way data bus with the CPU, CPU/ATA interface IC, memory stick interface IC,
display controller, 64MB flash memory and 128MB SD-RAM
18
D_GND
—
Ground terminal (for digital system)
19
VHOLD_1
—
Voltage holding terminal
20
NC
O
Not used
21
CS_N
I
Chip select signal input from the CPU
22
RD_N
I
Read strobe signal input from the CPU
23
WR_N
I
Write enable signal input from the CPU
24
VHOLD_2
—
Voltage holding terminal
25
DREQ1
O
DMA request signal output to the CPU
26
DREQ2
O
DMA request signal output terminal    Not used
27
DACK1
I
DMA acknowledge signal input from the CPU
28
DACK2
I
DMA acknowledge signal input terminal   Not used
29
INT1
O
Interrupt request signal output to the CPU/ATA interface IC
30
INT2
O
Interrupt request signal output terminal   Not used
31
TEST
I
For test terminal (normally fixed at “H”)
32
RESET_N
I
Reset signal input from the CPU    “L” : reset
33
NDP_SEL
I
Number of downstream port selection terminal
“L” : 1 downstream port, “H” : 2 downstream ports (fixed at “L” in this set)  
34
EOT
I
Not used 
35
D_GND
—
Ground terminal (for digital system)
36
D_SUSPEND
O
Internal device controller's suspend signal output terminal    Not used
37
D_WAKEUP
I
Wake up signal input terminal    Not used
38
GL_N
O
LED drive signal output terminal    Not used
39
D_VBUS
I
USB connect detection signal input terminal    Not used
40
H_WAKEUP
I
Wake up signal input terminal    Not used
41
CLKOUT
O
Clock output terminal (3 to 48MHz)    Not used
42
H_SUSPEND
O
Internal host controller's suspend signal output terminal    Not used
43
X1
I
System clock input terminal (6MHz)
44
X2
O
System clock output terminal (6MHz)
45
D_GND
—
Ground terminal (for digital system)
46
H_PSW1_N
O
Power on/off control signal output terminal    Not used
47
H_PSW2_N
O
Power on/off control signal output terminal    Not used
48
D_D–
I/O
Two-way data bus of USB data (–)    Not used
49
D_D+
I/O
Two-way data bus of USB data (+)    Not used
50
H_D1–
I/O
Two-way data bus of USB data (–)
51
H_D1+
I/O
Two-way data bus of USB data (+)
52
H_D2–
I/O
Two-way data bus of USB data (–)    Not used
53
H_D2+
I/O
Two-way data bus of USB data (+)    Not used
91
MEX-1HD
Pin No.
Pin Name
I/O
Description
54
H_OC1_N
I
Over current detection signal input terminal
55
H_OC2_N
I
Over current detection signal input terminal
56
VCC2
—
Power supply terminal (+3.3V)
57
A_GND
—
Ground terminal (for analog system)
58
VREG
O
+3.3V power output terminal
59, 60
A0, A1
I
Address signal input from the CPU
61
NC
O
Not used
62
D_GND
—
Ground terminal (for digital system)
63, 64
D0, D1
I/O
Two-way data bus with the CPU, CPU/ATA interface IC, memory stick interface IC,
display controller, 64MB flash memory and 128MB SD-RAM
92
MEX-1HD
•
 MAIN BOARD   IC5001    XC9572XL-10VQ44C-FL11 (DISPLAY CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
AI<1>
I
Address signal input from the CPU
2, 3
DI<15>, DI<14>
I/O
Two-way data bus with the CPU, CPU/ATA interface IC, memory stick interface IC,
USB interface IC, 64MB flash memory and 128MB SD-RAM
4
GND
—
Ground terminal
5 to 8
DI<13> to 
DI<10>
I/O
Two-way data bus with the CPU, CPU/ATA interface IC, memory stick interface IC,
USB interface IC, 64MB flash memory and 128MB SD-RAM
9
TDI
I
Not used
10
TMS
I
Not used
11
TCK
I
Not used
12 to 14
DI<9> to DI<7>
I/O
Two-way data bus with the CPU, CPU/ATA interface IC, memory stick interface IC,
USB interface IC, 64MB flash memory and 128MB SD-RAM
15
VCC
—
Power supply terminal (+3.3V)
16
DI<6>
I/O
Two-way data bus with the CPU, CPU/ATA interface IC, memory stick interface IC,
USB interface IC, 64MB flash memory and 128MB SD-RAM
17
GND
—
Ground terminal
18 to 23
DI<5> to DI<0>
I/O
Two-way data bus with the CPU, CPU/ATA interface IC, memory stick interface IC,
USB interface IC, 64MB flash memory and 128MB SD-RAM
24
TDO
O
Not used
25
GND
—
Ground terminal
26
VCC
—
Power supply terminal (+3.3V)
27
NC
I/O
Not used
28
SCKO
O
Serial data transfer clock signal output to the fluorescent indicator tube and LED controller
29
SOO
O
Serial data output to the fluorescent indicator tube and LED controller
30
FL_DONI
I
Fluorescent indicator tube driver power supply on/off control signal input terminal
“H”: fluorescent indicator tube on
31
LATO
O
Serial data latch pulse signal output to the fluorescent indicator tube and LED controller
32
RSTI
I
System reset signal input from the system controller
33
DACKI
I
Acknowledge signal input from the CPU
34
BKO
O
Bit clock signal output to the fluorescent indicator tube
35
VCC
—
Power supply terminal (+3.3V)
36 to 39
NC
I/O
Not used
40
DREQO
O
DMA request signal output to the CPU
41
WEI
I
Write enable signal input from the CPU
42
CS6I
I
Chip select signal input from the CPU
43
MCKI
I
Clock signal input from the oscillator
44
AI<0>
I
Address signal input from the CPU
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