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53

•

Pin No.

Pin Name

I/O

Description

1 to 5

TIN3 to TIN7

I/O

Input of the 4

×

8 matrix test keys (“L” is always output, except in test mode)     Not used (open)

6

LOAD

O

Loading motor control signal output to the motor driver (IC305)    “H” active    *1

7

EJECT

O

Loading motor control signal output to the motor driver (IC305)    “H” active    *1

8, 9

—

O

Not used (open)

10

MDMON

O

Power supply on/off control signal output of the power controller (IC101)    “H”: power on

11

E-SW

I

Inputs a disc loading completion detect switch detection signal
“L”: When completed of a disc loading operation

12

AG-OK

O

Output of aging status in test mode   “L”: under aging,  “H”: aging completed    Not used (open)

13

ADJ-OK

O

Output of status when aging completed in test mode    “L”: aging NG, “H”: aging OK
Not used (open)

14 to 17

—

O

Not used (open)

18

DFCTSEL

I

Select whether defect function is used for the CXD2662R (IC301)
“L”: used this function , “H”: not used this function (fixed at “H” in this set)

19

DPLLSEL

I

Select whether double PLL function is used for the CXD2662R (IC301)
“L”: used this function , “H”: not used this function (fixed at “H” in this set)

20

EMPHSEL

I

Select whether emphasis signal output from pin or unilink data
“L”: outputs from both pin and unilink data, “H”: output from pin only (fixed at “H” in this set)

21

LOCK

O

Mini-disc lock detection signal output to the system controller (IC501)

22

—

O

Not used (open)

23

2M/4M

I

Select whether D-RAM capacitance 2M bit or 4M bit    “L”: 4M bit (external D-RAM) , “H”: 2M
bit (internal D-RAM of CXD2652AR) (fixed at “L” in this set)

24, 25

—

O

Not used (open)

26

MNT0

I

Focus OK signal input from the CXD2662R (IC301)
“H” is input when focus is on (“L”: NG)

27

MNT1

I

Track jump detection signal input from the CXD2662R (IC301)

28

MNT2

I

Busy monitor signal input from the CXD2662R (IC301)

29

MNT3

I

Spindle servo lock status monitor signal input from the CXD2662R (IC301)

30

RESET

I

System reset signal input from the system controller (IC501) and reset signal generator (IC502)
“L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”

31

EXTAL

I

Main system clock input terminal (10 MHz)

32

XTAL

O

Main system clock output terminal (10 MHz)

33

VSS

—

Ground terminal

34

TX

O

Sub system clock output terminal (32.768 kHz)    Not used (open)

35

TEX

I

Sub system clock input terminal (32.768 kHz)    Not used (fixed at “L”)

36

AVSS

—

Ground terminal (for A/D converter)

37

AVREF

I

Reference voltage input terminal (+5V) (for A/D converter)

38

INIT

I

Initial reset signal input terminal (A/D input) (fixed at “H”)

39

TEMP

I

Temperature sensor (TH501) input terminal (A/D input)

40

ACNT

I

Select the number of load/eject aging times (A/D input)
0h – 54h (30 times), 55h – 0A9h (20 times), 0AAh – 0FFh (10 times)

41

DO-SEL

I

Select the digital output bits (A/D input)

42

EE-CS

O

Chip select signal output to the external EEPROM device    Not used (open)

43

EE-CKO

O

Serial data transfer clock signal output to the external EEPROM device    Not used (open)

44

EE-SIO

I/O

Two way data bus with the external EEPROM device    Not used (open)

45

MD-SO

O

Writing serial data signal output to the CXD2662R (IC301) and CXA2523AR (IC302)

54

Pin No.

Pin Name

I/O

Description

46

LINKOFF

O

Unilink on/off control signal output for the SONY bus    “H”: link off    Not used (open)

47

UNIREQ

O

Data request signal output terminal (for SONY bus)    “H”: request on    Not used (open)

48

UNICKIO

I/O

Serial clock signal input from the system controller (IC501) or serial clock signal output to the
system controller (IC501) and SONY bus interface (IC601)

49

UNISI

I

Serial data input from the SONY bus interface (IC601)

50

UNISO

O

Serial data output to the SONY bus interface (IC601)

51

MD-CKO

O

Serial data transfer clock signal output to the CXD2662R (IC301) and CXA2523AR (IC302)

52

MD-SI

I

Reading serial data signal input from the CXD2662R (IC301)

53

—

O

Not used (open)

54

SENS

I

Internal status (SENSE) input from the CXD2662R (IC301)

55

CC-XINT

I

Interrupt status input from the CXD2662R (IC301)

56

LIMIT-IN

I

Detection input from the sled limit-in detect switch
The optical pick-up is inner position when “L”

57

EJT-OK

I

Front panel open detection signal input from the system controller (IC501)
“L”: eject possible

58

ERROR-PWM

O

PWM error monitor output terminal (C1and ATER is output when test mode)    Not used (open)

59

MD-RST

O

Reset signal output to the PCM1718E (IC101), CXD2662R (IC301) and BH6518FS (IC303)
“L”: reset

60

BU-IN

I

Battery detect signal input from the SONY bus interface (IC601) and battery check circuit
“H”: battery on

61

BUS-ON

I

SONY bus on/off control signal input from the system controller (IC501)    “L”: bus on

62

SQSY

I

Subcode Q sync (SCOR) input from the CXD2662R (IC301)
“L” is input every 13.3 msec    Almost all, “H” is input

63

C-SW

I

Inputs a disc loading start or a disc eject completion detect switch detection signal
“L”: When loading start or eject completed of a disc loading operation

64

MD-LAT

O

Serial data latch pulse signal output to the CXD2662R (IC301) and CXA2523AR (IC302)

65

MD-ON

O

Power supply on/off control signal output of the MD mechanism deck section main power supply
“H”: power on

66

DEEMP

O

De-emphasis on/off control signal output to the PCM1718E (IC101)    “H”: de-emphasis on

67

A-MUTE

O

Power amplifier muting on/off control signal output to the power amplifier (IC309) and audio line
muting on/off control signal output    “H”: muting on

68

—

O

Not used (open)

69

TSTCKO

O

Output of clock signal for the test mode display    Not used (open)

70

TSTSO

O

Output of data for the test mode display    Not used (open)

71

TSTMOD

I

Setting terminal for the test mode    “L”: test mode, “H”: normal mode

72

VCC

—

Power supply terminal (+5V)

73

NC

I

Not used (fixed at “H”)

74 to 77

TOUT0 to TOUT3

O

Output of the 4

×

8 matrix test keys     Not used (open)

78 to 80

TIN0 to TIN2

I/O

Input of the 4

×

8 matrix test keys (“L” is always output, except in test mode)     Not used (open)

*1  Loading motor (M903) control

LOAD (pin 6)

“H”

“L”

“H”

“L”

EJECT (pin 7)

“L”

“H”

“H”

“L”

Terminal

Operation

IN

OUT

BRAKE

STOP

55

•

Pin No.

Pin Name

I/O

Description

1 to 4

NCO

O

Not used (open)

5

ATT

O

Power amplifier muting on/off control signal output to the power amplifier (IC309) and audio line
muting on/off control signal output    “H”: muting on

6

SYSRST

O

Reset signal output to the MD mechanism controller (IC501) SONY bus interface (IC601)
“L”: reset

7 to 9

NCO

O

Not used (open)

10

EEP SIO

I/O

Two-way data EEPROM bus with the FM/AM tuner unit (TUX201)

11

EEP CKO

O

EEPROM bus clock signal output to the FM/AM tuner unit (TUX201)

12

RX

I

Input terminal for UART transfer data when writing into internal flash memory data

13

TX

O

Output terminal for UART transfer data when writing into internal flash memory data

14

BUS- ON

O

Bus on/off control signal output to the MD mechanism controller (IC501),  SONY bus interface
(IC601) and display controller (IC702)    “L”: bus on

15

BEEP

O

Beep sound drive signal output terminal

16

TEL-ATT

I

Telephone muting signal input terminal    “H”: muting on

17

UNISI

I

Serial data input from the SONY bus interface (IC601)

18

UNISO

O

Serial data output to the SONY bus interface (IC601)

19

UNICLK

I/O

Serial clock signal output to the MD mechanism controller (IC501), SONY bus interface (IC601)
and display controller (IC702) or serial clock signal input from the MD mechanism controller
(IC501)

20 to 23

NCO

O

Not used (open)

24

SIRCS

I

Sircs remote control signal input from the SIRCS controller (IC801)

25 to 30

NCO

O

Not used (open)

31

E-VOL-ATT

O

Pre amplifier muting on/off control signal output to the TDA7406T (IC305)
“L”: muting on

32

NCO

O

Not used (open)

33

VSS

—

Ground terminal

34

C

—

Connected to coupling capacitor for the power supply

35, 36

NCO

O

Not used (open)

37

SHIFT

O

Oscillation frequency shift signal output to the power controller (IC101)

38

DVCC

—

Power supply terminal (+5V) (for D/A converter)

39

DVSS

—

Ground terminal (for D/A converter)

40

FR_CTRL

O

Reference voltage control signal output for front panel open/close motor driver (IC651)

41

NCO

O

Not used (open)

42

AVCC

—

Power supply terminal (+5V) (for A/D converter)

43

AVRH

I

Reference voltage (+5V) input terminal (for A/D converter)

44

AVRL

I

Reference voltage (0V) input terminal (for A/D converter)

45

AVSS

—

Ground terminal (for A/D converter)

46

KEY-IN0

I

Key input terminal (A/D input) (LSW10, LSW13, LSW15, LSW18, LSW20, LSW22, S4, S10 to
S15) 6,. m, TA, DISC –, DISC +, > M, Z, ENTER, LIST, MENU, SOUND, DSO,
EQ7 keys input

47

KEY-IN1

I

Key input terminal (A/D input) (LSW1,LSW2, LSW5 to LSW9, LSW11, LSW12, S2, S3, S7 to
S9) –, SOURCE, +, AF, REP 1, SHUF 2, 3, 5, 4, CLOSE, MODE, OFF, SCRL, DSPL PTY keys
input

48

RC-IN0

I

Rotary remote commander key input terminal (A/D input)

49

NCO

O

Not used (open)

50

QUAL

I

Noise level detection signal input at SEEK mode (A/D input)

51

NCO

O

Not used (open)

52

MPTH

I

Multi-path detection signal input from the RDS decoder (IC202) (A/D input)

56

Pin No.

Pin Name

I/O

Description

53

S-METER

I

FM and AM signal meter voltage detection signal input from the FM/AM tuner unit (TUX201)
(A/D input)

54

VCC

—

Power supply terminal (+5V)

55

ST-BY

O

Standby on/off control signal output to the power amplifier (IC309)
“L”: standby mode, “H”: amp on

56

NS-MASK

O

Discharge control signal output for the noise detection circuit   “H”: discharge

57

DDC-ON

O

Power supply on/off control signal output of the power controller (IC101)    “H”: power on

58

CD_EJECT_OK

O

Front panel open detection signal output to the MD mechanism controller (IC501)
“L”: eject possible

59

CD_OPEN_REQ

I

Mini-disc lock detection signal input to the MD mechanism controller (IC501)

60

NCO

O

Not used (open)

61

OPEN-KEY

I

Open key (LSW60) input terminal    When “L” is input, open the front panel

62

NOSE-SW

I

Display panel attach detection signal input terminal    “L”: front panel is attached

63

VSS

—

Ground terminal

64

DETACH_SW

I

Display panel detach detection signal input terminal    “L”: front panel is detached

65

PWM

I

For frequency counting signal input teminal from the power controller (IC101)

66 to 68

NCO

O

Not used (open)

69

FLASH-W

I

Internal flash memory data write mode detection signal input terminal    “L”: data write mode

70

IIC-SDA

I/O

Two-way data IIC bus with the FM/AM tuner unit (TUX201), RDS decoder (IC202) and
TDA7406T (IC305)

71

IIC-SCL

O

IIC bus clock signal output to the FM/AM tuner unit (TUX201), RDS decoder (IC202) and
TDA7406T (IC305)

72

RC-IN1

I

Rotary remote commander shift key input terminal    “L”: shift key on

73

X1A

O

Sub system clock output terminal (32.768 kHz)

74

X0A

I

Sub system clock input terminal (32.768 kHz)

75

DAVN

I

Synchronized detection signal of RDS data block input from the RDS decoder (IC202)
“H”: active

76

NCO

O

Not used (open)

77

BUIN

I

Battery detection signal input from the SONY bus interface (IC601)
“L” is input at low voltage

78

NCO

O

Not used (open)

79

KEY_ACK

I

Input of acknowledge signal for the key entry    Acknowledge signal is input to accept function
and eject keys in the power off status    On at input of “H”

80

AD-ON

O

A/D converter power control signal output
When the KEY_ACK (pin ul) that controls reference voltage power for key A/D conversion
input is active, “L” is output from this terminal to enable the input

81

ACC IN

I

Accessory detect signal input terminal    “L”: accessory on

82

FLS_PWON

O

Display power supply on/off control signal output    “H”: display power on

83

P-ON

O

Audio power supply on/off control signal output    “H”: audio power on

84

TEST-IN

I

Setting terminal for the test mode    “L”: test mode, Normally: fixed at “H”

85

RAMBU

I

Internal RAM reset detection signal input from the reset signal generator (IC502)
Input terminal to check that RAM data are not destroyed due to low voltage
This checking is made within 100 msec after reset

86

HSTX

I

Hardware standby input terminal    “L”: hardware standby mode    Reset signal input in this set

87

MD2

I

Setting terminal for the CPU operational mode (fixed at “L” in this set)

88

MD1

I

Setting terminal for the CPU operational mode (fixed at “H” in this set)

89

MD0

I

Setting terminal for the CPU operational mode (fixed at “H” in this set)

90

RSTX

I

System reset signal input from the reset signal generator (IC502) and reset switch (SW901, S60)
“L”: reset    “L” is input for several 100 msec after power on, then it changes to “H”