Sony MDX-M690 Service Manual ▷ View online
49
MDX-M690
6-21.
IC PIN FUNCTION DESCRIPTION
•
SERVO BOARD IC301 CXD2662R
Pin No.
Pin Name
I/O
Description
1
MNT0 (FOK)
O
Focus OK signal output to the MD mechanism controller (IC501)
“H” is output when focus is on (“L”: NG)
“H” is output when focus is on (“L”: NG)
2
MNT1 (SHOCK)
O
Track jump detection signal output to the MD mechanism controller (IC501)
3
MNT2 (XBUSY)
O
Busy monitor signal output to the MD mechanism controller (IC501)
4
MNT3 (SLOCK)
O
Spindle servo lock status monitor signal output to the MD mechanism controller (IC501)
5
SWDT
I
Writing serial data signal input from the MD mechanism controller (IC501)
6
SCLK
I
Serial data transfer clock signal input from the MD mechanism controller (IC501)
7
XLAT
I
Serial data latch pulse signal input from the MD mechanism controller (IC501)
8
SRDT
O (3)
Reading serial data signal output to the MD mechanism controller (IC501)
9
SENS
O (3)
Internal status (SENSE) output to the MD mechanism controller (IC501)
10
XRST
I
Reset signal input from the MD mechanism controller (IC501) “L”: reset
11
SQSY
O
Subcode Q sync (SCOR) output to the MD mechanism controller (IC501)
“L” is output every 13.3 msec Almost all, “H” is output
“L” is output every 13.3 msec Almost all, “H” is output
12
DQSY
O
Digital In U-bit CD format subcode Q sync (SCOR) output terminal
“L” is output every 13.3 msec Almost all, “H” is output Not used (open)
“L” is output every 13.3 msec Almost all, “H” is output Not used (open)
13
RECP
I
Laser power selection signal input terminal
“L”: playback mode, “H”: recording mode (fixed at “L” in this set)
“L”: playback mode, “H”: recording mode (fixed at “L” in this set)
14
XINT
O
Interrupt status output to the MD mechanism controller (IC501)
15
TX
O
Recording data output enable signal input terminal
Writing data transmission timing input (Also serves as the magnetic head on/off output)
Not used (fixed at “L”)
Writing data transmission timing input (Also serves as the magnetic head on/off output)
Not used (fixed at “L”)
16
OSCI
I
System clock signal (1024Fs=45 MHz) input from the oscillator circuit
17
OSCO
O
System clock signal (1024Fs=45 MHz) output terminal Not used (open)
18
XTSL
I
Input terminal for the system clock frequency setting
“L”: 45.1584 MHz, “H”: 22.5792 MHz (fixed at “L” in this set)
“L”: 45.1584 MHz, “H”: 22.5792 MHz (fixed at “L” in this set)
19
DIN0
I
Digital audio signal input terminal when recording mode Not used (fixed at “L”)
20
DIN1
I
Digital audio signal input terminal when recording mode Not used (fixed at “L”)
21
DOUT
O
Digital audio signal output terminal when playback mode Not used
22
DADTAI
I
Recording data input terminal Not used (fixed at “L”)
23
LRCKI
I
L/R sampling clock signal (44.1 kHz) input terminal Not used (fixed at “L”)
24
XBCKI
I
Bit clock signal (2.8224 MHz) input terminal Not used (fixed at “L”)
25
ADDT
I
Recording data input terminal Not used (fixed at “L”)
26
DADT
O
Playback data output to the PCM1718E (IC101)
27
LRCK
O
L/R sampling clock signal (44.1 kHz) output to the PCM1718E (IC101)
28
XBCK
O
Bit clock signal (2.8224 MHz) output to the PCM1718E (IC101)
29
FS256
O
Clock signal (11.2896 MHz) output to the PCM1718E (IC101)
30
DVDD
—
Power supply terminal (+3.3V) (digital system)
31 to 34
A03 to A00
O
Address signal output to the D-RAM (IC307)
35
A10
O
Address signal output to the external D-RAM Not used (open)
36 to 40
A04 to A08
O
Address signal output to the D-RAM (IC307)
41
A11
O
Address signal output to the external D-RAM Not used (open)
42
DVSS
—
Ground terminal (digital system)
43
XOE
O
Output enable signal output to the D-RAM (IC307) “L” active
44
XCAS
O
Column address strobe signal output to the D-RAM (IC307) “L” active
45
A09
O
Address signal output to the D-RAM (IC307)
(DIGITAL SIGNAL PROCESSOR, DIGITAL SERVO PROCESSOR, EFM/ACIRC ENCODER/DECODER,
SHOCK PROOF MEMORY CONTROLLER, ATRAC ENCODER/DECODER)
SHOCK PROOF MEMORY CONTROLLER, ATRAC ENCODER/DECODER)
50
MDX-M690
Pin No.
Pin Name
I/O
Description
46
XRAS
O
Row address strobe signal output to the D-RAM (IC307) “L” active
47
XWE
O
Write enable signal output to the D-RAM (IC307) “L” active
48
D1
I/O
49
D0
I/O
50
D2
I/O
51
D3
I/O
52
MVCI
I
Digital in PLL oscillation input from the external VCO Not used (fixed at “L”)
53
ASYO
O
Playback EFM full-swing output terminal
54
ASYI
I (A)
Playback EFM asymmetry comparator voltage input terminal
55
AVDD
—
Power supply terminal (+3.3V) (analog system)
56
BIAS
I (A)
Playback EFM asymmetry circuit constant current input terminal
57
RFI
I (A)
Playback EFM RF signal input from the CXA2523AR (IC302)
58
AVSS
—
Ground terminal (analog system)
59
PCO
O (3)
Phase comparison output for master clock of the recording/playback EFM master PLL
60
FILI
I (A)
Filter input for master clock of the recording/playback master PLL
61
FILO
O (A)
Filter output for master clock of the recording/playback master PLL
62
CLTV
I (A)
Internal VCO control voltage input of the recording/playback master PLL
63
PEAK
I (A)
Light amount signal (RF/ABCD) peak hold input from the CXA2523AR (IC302)
64
BOTM
I (A)
Light amount signal (RF/ABCD) bottom hold input from the CXA2523AR (IC302)
65
ABCD
I (A)
Light amount signal (ABCD) input from the CXA2523AR (IC302)
66
FE
I (A)
Focus error signal input from the CXA2523AR (IC302)
67
AUX1
I (A)
Auxiliary signal (I
3
signal/temperature signal) input from the CXA2523AR (IC302)
68
VC
I (A)
Middle point voltage (+1.65V) input from the CXA2523AR (IC302)
69
ADIO
O (A)
Monitor output of the A/D converter input signal Not used (open)
70
AVDD
—
Power supply terminal (+3.3V) (analog system)
71
ADRT
I (A)
A/D converter operational range upper limit voltage input terminal (fixed at “H” in this set)
72
ADRB
I (A)
A/D converter operational range lower limit voltage input terminal (fixed at “L” in this set)
73
AVSS
—
Ground terminal (analog system)
74
SE
I (A)
Sled error signal input from the CXA2523AR (IC302)
75
TE
I (A)
Tracking error signal input from the CXA2523AR (IC302)
76
DCHG
I (A)
Connected to the +3.3V power supply
77
APC
I (A)
Error signal input for the laser automatic power control Not used (fixed at “L”)
78
ADFG
I
ADIP duplex FM signal (22.05 kHz
±
1 kHz) input from the CXA2523AR (IC302)
79
F0CNT
O
Filter f0 control signal output terminal Not used (open)
80
XLRF
O
Serial data latch pulse signal output terminal Not used (open)
81
CKRF
O
Serial data transfer clock signal output terminal Not used (open)
82
DTRF
O
Writing serial data output terminal Not used (open)
83
APCREF
O
Control signal output to the reference voltage generator circuit for the laser automatic power
control
control
84
TEST0
O
Input terminal for the test Not used (open)
85
TRDR
O
Tracking servo drive PWM signal (–) output to the BH6518FS (IC303)
86
TFDR
O
Tracking servo drive PWM signal (+) output to the BH6518FS (IC303)
87
DVDD
—
Power supply terminal (+3.3V) (digital system)
88
FFDR
O
Focus servo drive PWM signal (+) output to the BH6518FS (IC303)
89
FRDR
O
Focus servo drive PWM signal (–) output to the BH6518FS (IC303)
90
FS4
O
Clock signal (176.4 kHz) output terminal (X’tal system) Not used (open)
Two-way data bus with the D-RAM (IC307)
51
MDX-M690
Pin No.
Pin Name
I/O
Description
91
SRDR
O
Sled servo drive PWM signal (–) output to the BH6518FS (IC303)
92
SFDR
O
Sled servo drive PWM signal (+) output to the BH6518FS (IC303)
93
SPRD
O
Spindle servo drive PWM signal (–) output to the BH6518FS (IC303)
94
SPFD
O
Spindle servo drive PWM signal (+) output to the BH6518FS (IC303)
95
FGIN
I
96
TEST1
I
97
TEST2
I
98
TEST3
I
99
DVSS
—
Ground terminal (digital system)
100
EFMO
O
EFM signal output terminal when recording mode Not used (open)
* I (A) for analog input, O (3) for 3-state output, and O (A) for analog output in the column I/O.
Input terminal for the test (fixed at “L”)
52
MDX-M690
•
SERVO BOARD IC302 CXA2523AR (RF AMP, FOCUS/TRACKING ERROR AMP)
Pin No.
Pin Name
I/O
Description
1
I
I
I-V converted RF signal I input from the optical pick-up block detector
2
J
I
I-V converted RF signal J input from the optical pick-up block detector
3
VC
O
Middle point voltage (+1.65V) generation output terminal
4 to 9
A to F
I
Signal input from the optical pick-up detector
10
PD
I
Light amount monitor input from the optical pick-up block laser diode
11
APC
O
Laser amplifier output terminal to the automatic power control circuit
12
APCREF
I
Reference voltage input terminal for setting laser power
13
GND
—
Ground terminal
14
TEMPI
I
Connected to the temperature sensor Not used (open)
15
TEMPR
O
Output terminal for a temperature sensor reference voltage Not used (open)
16
SWDT
I
Writing serial data input from the MD mechanism controller (IC501)
17
SCLK
I
Serial data transfer clock signal input from the MD mechanism controller (IC501)
18
XLAT
I
Serial data latch pulse signal input from the MD mechanism controller (IC501)
19
XSTBY
I
Standby signal input terminal “L”: standby (fixed at “H” in this set)
20
F0CNT
I
Center frequency control voltage input terminal of internal circuit (BPF22, BPF3T, EQ) input
terminal
terminal
21
VREF
O
Reference voltage output terminal Not used (open)
22
EQADJ
I
Center frequency setting terminal for the internal circuit (EQ)
23
3TADJ
I
Center frequency setting terminal for the internal circuit (BPF3T)
24
VCC
—
Power supply terminal (+3.3V)
25
WBLADJ
I
Center frequency setting terminal for the internal circuit (BPF22)
26
TE
O
Tracking error signal output to the CXD2662R (IC301)
27
CSLED
I
Connected to the external capacitor for low-pass filter of the sled error signal
28
SE
O
Sled error signal output to the CXD2662R (IC301)
29
ADFM
O
FM signal output of the ADIP
30
ADIN
I
Receives a ADIP FM signal in AC coupling
31
ADAGC
I
Connected to the external capacitor for ADIP AGC
32
ADFG
O
ADIP duplex signal (22.05 kHz
±
1 kHz) output to the CXD2662R (IC301)
33
AUX
O
Auxiliary signal (I
3
signal/temperature signal) output terminal Not used (open)
34
FE
O
Focus error signal output to the CXD2662R (IC301)
35
ABCD
O
Light amount signal (ABCD) output to the CXD2662R (IC301)
36
BOTM
O
Light amount signal (RF/ABCD) bottom hold output to the CXD2662R (IC301)
37
PEAK
O
Light amount signal (RF/ABCD) peak hold output to the CXD2662R (IC301)
38
RF
O
Playback EFM RF signal output to the CXD2662R (IC301)
39
RFAGC
I
Connected to the external capacitor for RF auto gain control circuit
40
AGCI
I
Receives a RF signal in AC coupling
41
COMPO
O
User comparator output terminal Not used (open)
42
COMPP
I
User comparator input terminal Not used (fixed at “L”)
43
ADDC
I
Connected to the external capacitor for cutting the low band of the ADIP amplifier
44
OPO
O
User operational amplifier output terminal Not used (open)
45
OPN
I
User operational amplifier inversion input terminal Not used (fixed at “L”)
46
RFO
O
RF signal output
47
MORFI
I
Receives a MO RF signal in AC coupling
48
MORFO
O
MO RF signal output
Click on the first or last page to see other MDX-M690 service manuals if exist.