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– 44 –

40

DVSS

—

Ground terminal (digital system)

41

XOE

O

Output enable signal output to the D-RAM (IC307)    “L” active

42

XCAS

O

Column address strobe signal output to the D-RAM (IC307)    “L” active

43

A09

O

Address signal output to the external D-RAM    Not used (open)

44

XRAS

O

Row address strobe signal output to the D-RAM (IC307)    “L” active

45

XWE

O

Write enable signal output to the D-RAM (IC307)    “L” active

46

D1

I/O

47

D0

I/O

48

D2

I/O

49

D3

I/O

50

MVCI

I

Digital in PLL oscillation input from the external VCO    Not used (fixed at “L”)

51

ASYO

O

Playback EFM full-swing output terminal

52

ASYI

I (A)

Playback EFM asymmetry comparator voltage input terminal

53

AVDD

—

Power supply terminal (+3.3V) (analog system)

54

BIAS

I (A)

Playback EFM asymmetry circuit constant current input terminal

55

RFI

I (A)

Playback EFM RF signal input from the CXA2523R (IC302)

56

AVSS

—

Ground terminal (analog system)

57

PDO

O (3)

Phase comparison output for clock playback analog PLL of the playback EFM    Not used (open)

58

PCO

O (3)

Phase comparison output for master clock of the recording/playback EFM master PLL

59

FILI

I (A)

Filter input for master clock of the recording/playback master PLL

60

FILO

O (A)

Filter output for master clock of the recording/playback master PLL

61

CLTV

I (A)

Internal VCO control voltage input of the recording/playback master PLL

62

PEAK

I (A)

Light amount signal (RF/ABCD) peak hold input from the CXA2523R (IC302)

63

BOTM

I (A)

Light amount signal (RF/ABCD) bottom hold input from the CXA2523R (IC302)

64

ABCD

I (A)

Light amount signal (ABCD) input from the CXA2523R (IC302)

65

FE

I (A)

Focus error signal input from the CXA2523R (IC302)

66

AUX1

I (A)

Auxiliary signal (I

3

 signal/temperature signal) input terminal    Not used (fixed at “H”)

67

VC

I (A)

Middle point voltage (+1.65V) input from the CXA2523R (IC302)

68

ADIO

O (A)

Monitor output of the A/D converter input signal    Not used (open)

69

AVDD

—

Power supply terminal (+3.3V) (analog system)

70

ADRT

I (A)

A/D converter operational range upper limit voltage input terminal (fixed at “H” in this set)

71

ADRB

I (A)

A/D converter operational range lower limit voltage input terminal (fixed at “L” in this set)

72

AVSS

—

Ground terminal (analog system)

73

SE

I (A)

Sled error signal input from the CXA2523R (IC302)

74

TE

I (A)

Tracking error signal input from the CXA2523R (IC302)

75

AUX2

I (A)

Auxiliary signal input terminal    Light amount signal input from the CXA2523R (IC302)

76

DCHG

I (A)

Connected to the +3.3V power supply

77

APC

I (A)

Error signal input for the laser automatic power control    Not used (fixed at “L”)

78

ADFG

I

ADIP duplex FM signal (22.05 kHz 

±

 1 kHz) input from the CXA2523R (IC302)

79

F0CNT

O

Filter f0 control signal output terminal    Not used (open)

80

XLRF

O

Serial data latch pulse signal output terminal    Not used (open)

81

CKRF

O

Serial data transfer clock signal output terminal    Not used (open)

82

DTRF

O

Writing serial data output terminal    Not used (open)

83

APCREF

O

Control signal output to the reference voltage generator circuit for the laser automatic power
control

84

LDDR

O

PWM signal output for the laser automatic power control    Not used (open)

85

TRDR

O

Tracking servo drive PWM signal (–) output to the BH6511FS (IC303)

86

TFDR

O

Tracking servo drive PWM signal (+) output to the BH6511FS (IC303)

Two-way data bus with the D-RAM (IC307)

– 45 –

87

DVDD

—

Power supply terminal (+3.3V) (digital system)

88

FFDR

O

Focus servo drive PWM signal (+) output to the BH6511FS (IC303)

89

FRDR

O

Focus servo drive PWM signal (–) output to the BH6511FS (IC303)

90

FS4

O

Clock signal (176.4 kHz) output terminal (X’tal system)    Not used (open)

91

SRDR

O

Sled servo drive PWM signal (–) output to the BH6511FS (IC303)

92

SFDR

O

Sled servo drive PWM signal (+) output to the BH6511FS (IC303)

93

SPRD

O

Spindle servo drive PWM signal (–) output to the BH6511FS (IC303)

94

SPFD

O

Spindle servo drive PWM signal (+) output to the BH6511FS (IC303)

95

FGIN

I

Not used (fixed at “L”)

96

TEST1

I

97

TEST2

I

Input terminal for the test (fixed at “L”)

98

TEST3

I

99

DVSS

—

Ground terminal (digital system)

100

EFMO

O

EFM signal output terminal when recording mode    Not used (open)

* I (A) for analog input, O (3) for 3-state output, and O (A) for analog output in the column I/O.

– 46 –

•

1

I

I

I-V converted RF signal I input from the optical pick-up block detector

2

J

I

I-V converted RF signal J input from the optical pick-up block detector

3

VC

O

Middle point voltage (+1.65V) generation output terminal

4 to 9

A to F

I

Signal input from the optical pick-up detector

10

PD

I

Light amount monitor input from the optical pick-up block laser diode

11

APC

O

Laser amplifier output terminal to the automatic power control circuit

12

APCREF

I

Reference voltage input terminal for setting laser power

13

GND

—

Ground terminal

14

TEMPI

I

Connected to the temperature sensor    Not used (open)

15

TEMPR

O

Output terminal for a temperature sensor reference voltage    Not used (open)

16

SWDT

I

Writing serial data input from the MD mechanism controller (IC501)

17

SCLK

I

Serial data transfer clock signal input from the MD mechanism controller (IC501)

18

XLAT

I

Serial data latch pulse signal input from the MD mechanism controller (IC501)

19

XSTBY

I

Standby signal input terminal    “L”: standby (fixed at “H” in this set)

20

F0CNT

I

Center frequency control voltage input terminal of internal circuit (BPF22, BPF3T, EQ) input
terminal

21

VREF

O

Reference voltage output terminal    Not used (open)

22

EQADJ

I

Center frequency setting terminal for the internal circuit (EQ)

23

3TADJ

I

Center frequency setting terminal for the internal circuit (BPF3T)

24

VCC

—

Power supply terminal (+3.3V)

25

WBLADJ

I

Center frequency setting terminal for the internal circuit (BPF22)

26

TE

O

Tracking error signal output to the CXD2652AR (IC301)

27

CSLED

I

Connected to the external capacitor for low-pass filter of the sled error signal

28

SE

O

Sled error signal output to the CXD2652AR (IC301)

29

ADFM

O

FM signal output of the ADIP

30

ADIN

I

Receives a ADIP FM signal in AC coupling

31

ADAGC

I

Connected to the external capacitor for ADIP AGC

32

ADFG

O

ADIP duplex signal (22.05 kHz 

±

 1 kHz) output to the CXD2652AR (IC301)

33

AUX

O

Auxiliary signal (I

3

 signal/temperature signal) output terminal    Not used (open)

34

FE

O

Focus error signal output to the  CXD2652AR (IC301)

35

ABCD

O

Light amount signal (ABCD) output to the CXD2652AR (IC301)

36

BOTM

O

Light amount signal (RF/ABCD) bottom hold output to the CXD2652AR (IC301)

37

PEAK

O

Light amount signal (RF/ABCD) peak hold output to the CXD2652AR (IC301)

38

RF

O

Playback EFM RF signal output to the CXD2652AR (IC301)

39

RFAGC

I

Connected to the external capacitor for RF auto gain control circuit

40

AGCI

I

Receives a RF signal in AC coupling

41

COMPO

O

User comparator output terminal    Not used (open)

42

COMPP

I

User comparator input terminal    Not used (fixed at “L”)

43

ADDC

I

Connected to the external capacitor for cutting the low band of the ADIP amplifier

44

OPO

O

User operational amplifier output terminal    Not used (open)

45

OPN

I

User operational amplifier inversion input terminal    Not used (fixed at “L”)

46

RFO

O

RF signal output terminal

47

MORFI

I

Receives a MO RF signal in AC coupling

48

MORFO

O

MO RF signal output terminal

– 47 –

•

1 to 5

TIN3 to TIN7

I/O

Input of the 4

×

8 matrix test keys (“L” is always output, except in test mode)     Not used (open)

6

LOAD

O

Loading motor control signal output to the motor driver (IC305)    *1

7

EJECT

O

Loading motor control signal output to the motor driver (IC305)    *1

8, 9

NCO

O

Not used (open)

10

MDMON

O

Power supply on/off control signal output of the MD mechanism deck section main power supply
and loading motor drive (IC305) power supply    “H”: power on

11

E-SW

I

Inputs the disc loading completion detect switch (S902) detection signal
“L”: When completed of the disc loading operation

12

AG-OK

O

Output of aging status in test mode    “H”: aging completed, “L”: under aging    Not used (open)

13

ADJ-OK

O

Output of status when aging completed in test mode    “H”: aging OK, “L”: aging NG
Not used (open)

14 to 17

NCO

O

Not used (open)

18

DFCTSEL

I

Select whether defect function is used for the CXD2652AR (IC301)
“H”: not used this function, “L”: used this function (fixed at “H” in this set)

19

DPLLSEL

I

Select whether digital pll function is used for the CXD2652AR (IC301)
“H”: not used this function, “L”: used this function (fixed at “H” in this set)

20

EMPHSEL

I

Select whether emphasis signal output from pin or unilink data
“H”: output from pin only, “L”: outputs from both pin and unilink data    Not used (open)

21

LOCK

O

Mini-disc lock detection signal output to the master controller (IC700)    “H”: lock

22

NCO

O

Not used (open)

23

2M/4M

I

Select whether D-RAM capacitance 2M bit or 4M bit    “H”: 2M bit (internal D-RAM of
CXD2652AR), “L”: 4M bit (external D-RAM) (fixed at “L” in this set)

24, 25

NCO

O

Not used (open)

26

MNT0

I

Focus OK signal input from the CXD2652AR (IC301)
“H” is input when focus is on (“L”: NG)

27

MNT1

I

Track jump detection signal input from the CXD2652AR (IC301)

28

MNT2

I

Monitor 2 signal input from the CXD2652AR (IC301)

29

MNT3

I

Monitor 3 signal input from the CXD2652AR (IC301)

30

RESET

I

System reset signal input from the master controller (IC700), reset signal generator (IC801) and
reset switch (S900)    “L”: reset    For several hundreds msec. after the power supply rises, “L” is
input, then it changes to “H”

31

EXTAL

O

Main system clock output terminal (10 MHz)

32

XTAL

I

Main system clock input terminal (10 MHz)

33

VSS

—

Ground terminal

34

TX

O

Sub system clock output terminal (32.768 kHz)    Not used (open)

35

TEX

I

Sub system clock input terminal (32.768 kHz)    Not used (fixed at “L”)

36

AVSS

—

Ground terminal (for A/D converter)

37

AVREF

I

Reference voltage input terminal (+5V) (for A/D converter)

38

INIT

I

Initial reset signal input terminal (A/D input) (fixed at “H”)

39

TEMP

I

Temperature sensor (TH501) input terminal (A/D input)

40

ACNT

I

Select the number of load/eject aging times (A/D input)
0H – 54H (30 times), 55H – OA9H (20 times), OAAH – OFFH (10 times)

41

DO-SEL

I

Select the digital output bits (A/D input)

42

EE-CS

O

Chip select signal output to the external EEPROM device    Not used (open)

43

EE-CKO

O

Serial data transfer clock signal output to the external EEPROM device    Not used (open)

44

EE-SIO

I/O

Two way data bus with the external EEPROM device    Not used (open)

45

MD-SO

O

Writing serial data signal output to the CXD2652AR (IC301) and CXA2523R (IC302)

46

LINKOFF

O

Unilink on/off control signal output for the SONY bus    “H”: link off, “L”: link on