Sony MDX-C6500X Service Manual ▷ View online
21
Pin No.
Pin Name
I/O
Pin Description
91
SRDR
O
Sled servo drive PWM signal (–) output to the BH6511FS (IC303)
92
SFDR
O
Sled servo drive PWM signal (+) output to the BH6511FS (IC303)
93
SPRD
O
Spindle servo drive PWM signal (–) output to the BH6511FS (IC303)
94
SPFD
O
Spindle servo drive PWM signal (+) output to the BH6511FS (IC303)
95
FGIN
I
Not used (fixed at “L”)
96
TEST1
I
97
TEST2
I
Input terminal for the test (fixed at “L”)
98
TEST3
I
99
DVSS
—
Ground terminal (digital system)
100
EFMO
O
EFM signal output terminal when recording mode Not used (open)
* I (A) for analog input, O (3) for 3-state output, and O (A) for analog output in the column I/O.
22
• SERVO BOARD IC302 CXA2523AR (RF AMP, FOCUS/TRACKING ERROR AMP)
Pin No.
Pin Name
I/O
Pin Description
1
I
I
I-V converted RF signal I input from the optical pick-up block detector
2
J
I
I-V converted RF signal J input from the optical pick-up block detector
3
VC
O
Middle point voltage (+1.65 V) generation output terminal
4 – 9
A to F
I
Signal input from the optical pick-up detector
10
PD
I
Light amount monitor input from the optical pick-up block laser diode
11
APC
O
Laser amplifier output terminal to the automatic power control circuit
12
APCREF
I
Reference voltage input terminal for setting laser power from the CXD2652AR (IC301)
13
GND
—
Ground terminal
14
TEMPI
I
Connected to the temperature sensor Not used (open)
15
TEMPR
O
Output terminal for a temperature sensor reference voltage Not used (open)
16
SWDT
I
Writing serial data input from the MD mechanism controller (IC501)
17
SCLK
I
Serial data transfer clock signal input from the MD mechanism controller (IC501)
18
XLAT
I
Serial data latch pulse signal input from the MD mechanism controller (IC501)
19
XSTBY
I
Standby signal input terminal “L”: standby (fixed at “H” in this set)
20
F0CNT
I
Center frequency control voltage input terminal of internal circuit
(BPF22, BPF3T, EQ) input terminal
21
VREF
O
Reference voltage output terminal Not used (open)
22
EQADJ
I
Center frequency setting terminal for the internal circuit (EQ)
23
3TADJ
I
Center frequency setting terminal for the internal circuit (BPF3T)
24
VCC
—
Power supply terminal (+3.3 V)
25
WBLADJ
I
Center frequency setting terminal for the internal circuit (BPF22)
26
TE
O
Tracking error signal output to the CXD2652AR (IC301)
27
CSLED
I
Connected to the external capacitor for low-pass filter of the sled error signal
28
SE
O
Sled error signal output to the CXD2652AR (IC301)
29
ADFM
O
FM signal output of the ADIP
30
ADIN
I
Receives a ADIP FM signal in AC coupling
31
ADAGC
I
Connected to the external capacitor for ADIP AGC
32
ADFG
O
ADIP duplex signal (22.05 kHz ± 1 kHz) output to the CXD2652AR (IC301)
33
AUX
O
Auxiliary signal (I3 signal/temperature signal) output terminal Not used (open)
34
FE
O
Focus error signal output to the CXD2652AR (IC301)
35
ABCD
O
Light amount signal (ABCD) output to the CXD2652AR (IC301)
36
BOTM
O
Light amount signal (RF/ABCD) bottom hold output to the CXD2652AR (IC301)
37
PEAK
O
Light amount signal (RF/ABCD) peak hold output to the CXD2652AR (IC301)
38
RF
O
Playback EFM RF signal output to the CXD2652AR (IC301)
39
RFAGC
I
Connected to the external capacitor for RF auto gain control circuit
40
AGCI
I
Receives a RF signal in AC coupling
41
COMPO
O
User comparator output terminal Not used (open)
42
COMPP
I
User comparator input terminal Not used (fixed at “L”)
43
ADDC
I
Connected to the external capacitor for cutting the low band of the ADIP amplifier
44
OPO
O
User operational amplifier output terminal Not used (open)
45
OPN
I
User operational amplifier inversion input terminal Not used (fixed at “L”)
46
RFO
O
RF signal output terminal
47
MORFI
I
Receives a MO RF signal in AC coupling
48
MORFO
O
MO RF signal output terminal
23
• SERVO BOARD IC501 CXP84340-217Q (MD MECHANISM CONTROLLER)
Pin No.
Pin Name
I/O
Pin Description
1 – 5
TIN3 to TIN7
I/O
Input of the 4
×
8 matrix test keys (“L” is always output, except in test mode)
Not used (open)
6
LOAD
O
Loading motor control signal output to the loading motor drive (IC305) “H” active *1
7
EJECT
O
Loading motor control signal output to the loading motor drive (IC305) “H” active *1
8, 9
NCO
O
Not used (open)
10
MDMON
O
Power supply on/off control signal output of the MD mechanism deck section main
power supply and loading motor drive (IC305) power supply “H”: power on
11
E-SW
I
Inputs the disc loading completion detect switch detection signal
“L”: When completed of the disc loading operation
12
AG-OK
O
Output of aging status in test mode “L”: under aging, “H”: aging completed
Not used (open)
13
ADJ-OK
O
Output of status when aging completed in test mode “L”: aging NG, “H”: aging OK
Not used (open)
14 – 17
NCO
O
Not used (open)
18
DFCTSEL
I
Select whether defect function is used for the CXD2652AR (IC301)
“L”: used this function , “H”: not used this function (fixed at “H” in this set)
19
DPLLSEL
I
Select whether digital PLL function is used for the CXD2652AR (IC301)
“L”: used this function , “H”: not used this function (fixed at “H” in this set)
Select whether emphasis signal output from pin or unilink data
20
EMPHSEL
I
“L”: outputs from both pin and unilink data, “H”: output from pin only
(fixed at “H” in this set)
21
LOCK
O
Mini-disc lock detection signal output to the liquid crystal display driver “H”: lock
CLV lock status input in test mode
22
NCO
O
Not used (open)
23
2M/4M
I
Select whether D-RAM capacitance 2M bit or 4M bit “L”: 4M bit (external D-RAM),
“H”: 2M bit (internal D-RAM of CXD2652AR) (fixed at “L” in this set)
24, 25
NCO
O
Not used (open)
26
MNT0
I
Focus OK signal input from the CXD2652AR (IC301)
“H” is input when focus is on (“L”: NG)
27
MNT1
I
Track jump detection signal input from the CXD2652AR (IC301)
28
MNT2
I
Busy monitor signal input from the CXD2652AR (IC301)
29
MNT3
I
Spindle servo lock status monitor signal input from the CXD2652AR (IC301)
System reset signal input from the master controller (IC801), reset signal generator
30
RESET
I
(IC902) and reset switch (S900) “L”: reset For several hundreds msec. after the
power supply rises, “L” is input, then it changes to “H”
31
EXTAL
O
Main system clock output terminal (10 MHz)
32
XTAL
I
Main system clock input terminal (10 MHz)
33
VSS
—
Ground terminal
34
TX
O
Sub system clock output terminal (32.768 kHz) Not used (open)
35
TEX
I
Sub system clock input terminal (32.768 kHz) Not used (fixed at “L”)
36
AVSS
—
Ground terminal (for A/D converter)
37
AVREF
I
Reference voltage input terminal (+5 V) (for A/D converter)
38
INIT
I
Initial reset signal input terminal (A/D input) (fixed at “H”)
39
TEMP
I
Temperature sensor (TH501) input terminal (A/D input)
40
ACNT
I
Select the number of load/eject aging times (A/D input) 0H – 54H (30 times),
55H – OA9H (20 times), OAAH – OFFH (10 times) (fixed at “L”)
41
DO-SEL
I
Select the digital output bits (A/D input)
42
EE-CS
O
Chip select signal output to the external EEPROM device Not used (open)
43
EE-CKO
O
Serial data transfer clock signal output to the external EEPROM device Not used (open)
44
EE-SIO
I/O
Two way data bus with the external EEPROM device Not used (open)
45
MD-SO
O
Writing serial data signal output to the CXD2652AR (IC301) and CXA2523AR (IC302)
24
Pin No.
Pin Name
I/O
Pin Description
46
LINKOFF
O
Unilink on/off control signal output for the SONY bus “L”: link on, “H”: link off
47
UNIREQ
O
Data request signal output terminal (for SONY bus) “H”: request on Not used (open)
48
UNICKIO
I/O
Serial clock signal input from the master controller (IC801) or serial clock signal
output to the SONY bus interface (IC802) and master controller (IC801) (for SONY bus)
49
UNISI
I
Serial data input from the SONY bus interface (IC802)
50
UNISO
O
Serial data output to the SONY bus interface (IC802)
51
MD-CKO
O
Serial data transfer clock signal output to the CXD2652AR (IC301) and
CXA2523AR (IC302)
52
MD-SI
I
Reading serial data signal input from the CXD2652AR (IC301)
53
NCO
O
Not used (open)
54
SENS
I
Internal status (SENSE) input from the CXD2652AR (IC301)
55
CC-XINT
I
Interrupt status input from the CXD2652AR (IC301)
56
LIMIT-IN
I
Detection input from the sled limit-in detect switch
The optical pick-up is inner position when “L”
57
EJT-KEY
I
Eject request signal input terminal “L”: eject on Not used (fixed at “H”)
58
ERROR-PWM
O
PWM error monitor output terminal (C1and ATER is output when test mode)
Not used (open)
59
MD-RST
O
Reset signal output to the CXD2652AR (IC301) and BH6511FS (IC303) “L”: reset
60
BU-IN
I
Battery detect signal input from the SONY bus interface and battery check circuit
“H”: battery on
61
BUS-ON
I
SONY bus on/off control signal input from the master controller (IC801) “L”: bus on
62
SQSY
I
Subcode Q sync (SCOR) input from the CXD2652AR (IC301)
“L” is input every 13.3 msec Almost all, “H” is input
63
C-SW
I
Inputs the disc loading start or disc eject completion detect switch detection signal
“L”: When start or eject completed of the disc loading operation
64
MD-LAT
O
Serial data latch pulse signal output to the CXD2652AR (IC301) and
CXA2523AR (IC302)
65
MD-ON
O
Power supply on/off control signal output of the MD mechanism deck section main
power supply “H”: power on
66
DEEMP
O
Emphasis on/off control signal output to the master controller (IC801)
“H”: emphasis on
67
A-MUTE
O
Audio muting on/off control signal output terminal
68
NCO
O
Not used (open)
69
TSTCKO
O
Output of clock signal for the test mode display Not used (open)
70
TSTSO
O
Output of data for the test mode display Not used (open)
71
TSTMOD
I
Setting terminal for the test mode “L”: test mode, “H”: normal mode
72
VCC
—
Power supply terminal (+5 V)
73
NIL
I
Not used (fixed at “H”)
74 – 77
TOUT0 to TOUT3
O
Output of the 4
×
8 matrix test keys Not used (open)
78 – 80
TIN0 to TIN2
I/O
Input of the 4
×
8 matrix test keys (“L” is always output, except in test mode)
Not used (open)
*1 Loading motor (M903) control
Operation
IN
OUT
BRAKE
STOP
Terminal
LOAD (pin 6)
“H”
“L”
“H”
“L”
EJECT (pin 7)
“L”
“H”
“H”
“L”
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