Sony MDX-C6500X Service Manual ▷ View online
17
2-11. CHUCKING ARM ASSY
2-12. OPTICAL PICK-UP (KMS-241C/J1RP)
2
chucking arm assy
1
holder assy
6
bearing (SL)
5
feed screw assy
3
K2 x 3
2
shaft (OPTL)
1
K2 x 3
7
optical pick-up
(KMS-241C/J1RP)
(KMS-241C/J1RP)
4
B2 x 3
18
2-13. SL MOTOR ASSY (SLED) (M902)/SP MOTOR ASSY (SPINDLE) (M901)
4
P1.7 x 1.8
5
bracket (SL)
9
P1.7 x 1.8
0
bracket (SP)
qa
SP motor assy
(spindle) (M901)
7
B2 x 3
2
PSW2 x 8
3
SENSOR board
1
Remove solders
of motors (M901, 902).
of motors (M901, 902).
8
base (SL)
6
SL motor ass’y
(sled) (M902)
(sled) (M902)
19
3-1. IC PIN DESCRIPTIONS
• SERVO BOARD IC301 CXD2652AR
(DIGITAL SIGNAL PROCESSOR, DIGITAL SERVO PROCESSOR, EFM/ACIRC ENCODER/DECODER,
SHOCK PROOF MEMORY CONTROLLER, ATRAC ENCODER/DECODER, 2M BIT D-RAM)
SHOCK PROOF MEMORY CONTROLLER, ATRAC ENCODER/DECODER, 2M BIT D-RAM)
Pin No.
Pin Name
I/O
Pin Description
1
MNT0
O
Focus OK signal output to the MD mechanism controller (IC501)
“H” is output when focus is on (“L”: NG)
2
MNT1
O
Track jump detection signal output to the MD mechanism controller (IC501)
3
MNT2
O
Busy monitor signal output to the MD mechanism controller (IC501)
4
MNT3
O
Spindle servo lock status monitor signal output to the MD mechanism controller (IC501)
5
SWDT
I
Writing serial data signal input from the MD mechanism controller (IC501)
6
SCLK
I
Serial data transfer clock signal input from the MD mechanism controller (IC501)
7
XLAT
I
Serial data latch pulse signal input from the MD mechanism controller (IC501)
8
SRDT
O (3)
Reading serial data signal output to the MD mechanism controller (IC501)
9
SENS
O (3)
Internal status (SENSE) output to the MD mechanism controller (IC501)
10
XRST
I
Reset signal input from the MD mechanism controller (IC501) “L”: reset
11
SQSY
O
Subcode Q sync (SCOR) output to the MD mechanism controller (IC501)
“L” is output every 13.3 msec Almost all, “H” is output
12
DQSY
O
Digital In U-bit CD format subcode Q sync (SCOR) output terminal
“L” is output every 13.3 msec Almost all, “H” is output Not used (open)
13
RECP
I
Laser power selection signal input terminal
“L”: playback mode, “H”: recording mode (fixed at “L” in this set)
14
XINT
O
Interrupt status output to the MD mechanism controller (IC501)
Recording data output enable signal input terminal
15
TX
I
Writing data transmission timing input (Also serves as the magnetic head on/off output)
Not used (fixed at “L”)
16
OSCI
I
System clock signal (512Fs=22.5792 MHz) input
17
OSCO
O
System clock signal (512Fs=22.5792 MHz) output terminal Not used (open)
18
XTSL
I
Input terminal for the system clock frequency setting
“L”: 45.1584 MHz, “H”: 22.5792 MHz (fixed at “H” in this set)
19
RVDD
—
Power supply terminal (+3.3 V) (digital system)
20
RVSS
—
Ground terminal (digital system)
21
DIN
I
Digital audio signal input terminal when recording mode Not used (fixed at “L”)
22
DOUT
O
Digital audio signal output terminal when playback mode Not used (open)
23
ADDT
I
Recording data input terminal Not used (fixed at “L”)
24
DADT
O
Playback data output
25
LRCK
O
L/R sampling clock signal (44.1 kHz) output
26
XBCK
O
Bit clock signal (2.8224 MHz) output
27
FS256
O
Clock signal (11.2896 MHz) output terminal
28
DVDD
—
Power supply terminal (+3.3 V) (digital system)
29 – 32
A03 to A00
O
Address signal output to the D-RAM (IC307)
33
A10
O
Address signal output to the external D-RAM Not used (open)
34 – 38
A04 to A08
O
Address signal output to the D-RAM (IC307)
39
A11
O
Address signal output to the external D-RAM Not used (open)
40
DVSS
—
Ground terminal (digital system)
41
XOE
O
Output enable signal output to the D-RAM (IC307) “L” active
42
XCAS
O
Column address strobe signal output to the D-RAM (IC307) “L” active
43
A09
O
Address signal output to the D-RAM (IC307)
44
XRAS
O
Row address strobe signal output to the D-RAM (IC307) “L” active
45
XWE
O
Write enable signal output to the D-RAM (IC307) “L” active
SECTION 3
DIAGRAMS
20
Pin No.
Pin Name
I/O
Pin Description
46
D1
I/O
47
D0
I/O
Two-way data bus with the D-RAM (IC307)
48
D2
I/O
49
D3
I/O
50
MVCI
I
Digital in PLL oscillation input from the external VCO Not used (fixed at “L”)
51
ASYO
O
Playback EFM full-swing output terminal
52
ASYI
I (A)
Playback EFM asymmetry comparator voltage input terminal
53
AVDD
—
Power supply terminal (+3.3 V) (analog system)
54
BIAS
I (A)
Playback EFM asymmetry circuit constant current input terminal
55
RFI
I (A)
Playback EFM RF signal input from the CXA2523AR (IC302)
56
AVSS
—
Ground terminal (analog system)
57
PDO
O (3)
Phase comparison output for clock playback analog PLL of the playback EFM
Not used (open)
58
PCO
O (3)
Phase comparison output for master clock of the recording/playback EFM master PLL
59
FILI
I (A)
Filter input for master clock of the recording/playback master PLL
60
FILO
O (A)
Filter output for master clock of the recording/playback master PLL
61
CLTV
I (A)
Internal VCO control voltage input of the recording/playback master PLL
62
PEAK
I (A)
Light amount signal (RF/ABCD) peak hold input from the CXA2523AR (IC302)
63
BOTM
I (A)
Light amount signal (RF/ABCD) bottom hold input from the CXA2523AR (IC302)
64
ABCD
I (A)
Light amount signal (ABCD) input from the CXA2523AR (IC302)
65
FE
I (A)
Focus error signal input from the CXA2523AR (IC302)
66
AUX1
I (A)
Auxiliary signal (I3 signal/temperature signal) input terminal Not used (fixed at “H”)
67
VC
I (A)
Middle point voltage (+1.65 V) input from the CXA2523AR (IC302)
68
ADIO
O (A)
Monitor output of the A/D converter input signal Not used (open)
69
AVDD
—
Power supply terminal (+3.3 V) (analog system)
70
ADRT
I (A)
A/D converter operational range upper limit voltage input terminal
(fixed at “H” in this set)
71
ADRB
I (A)
A/D converter operational range lower limit voltage input terminal
(fixed at “L” in this set)
72
AVSS
—
Ground terminal (analog system)
73
SE
I (A)
Sled error signal input from the CXA2523AR (IC302)
74
TE
I (A)
Tracking error signal input from the CXA2523AR (IC302)
75
AUX2
I (A)
Auxiliary signal input terminal Light amount signal input from the CXA2523AR (IC302)
76
DCHG
I (A)
Connected to the +3.3 V power supply
77
APC
I (A)
Error signal input for the laser automatic power control Not used (fixed at “L”)
78
ADFG
I
ADIP duplex FM signal (22.05 kHz ± 1 kHz) input from the CXA2523AR (IC302)
79
F0CNT
O
Filter f0 control signal output terminal Not used (open)
80
XLRF
O
Serial data latch pulse signal output terminal Not used (open)
81
CKRF
O
Serial data transfer clock signal output terminal Not used (open)
82
DTRF
O
Writing serial data output terminal Not used (open)
83
APCREF
O
Control signal output to the reference voltage generator circuit for the laser
automatic power control
84
LDDR
O
PWM signal output for the laser automatic power control Not used (open)
85
TRDR
O
Tracking servo drive PWM signal (–) output to the BH6511FS (IC303)
86
TFDR
O
Tracking servo drive PWM signal (+) output to the BH6511FS (IC303)
87
DVDD
—
Power supply terminal (+3.3 V) (digital system)
88
FFDR
O
Focus servo drive PWM signal (+) output to the BH6511FS (IC303)
89
FRDR
O
Focus servo drive PWM signal (–) output to the BH6511FS (IC303)
90
FS4
O
Clock signal (176.4 kHz) output terminal (X’tal system) Not used (open)
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