Sony MDX-66XLP Service Manual ▷ View online
13
MDX-66XLP
• SERVO BOARD IC200 CXD2662R (DIGITAL SERVO SIGNAL PROCESSOR, DIGITAL SIGNAL PROCESSOR)
Pin No.
Pin Name
I/O
Pin Description
1
MNT0 (FOK)
O
Focus OK signal output to the MD mechanism controller (IC600)
“H” is output when focus is on (“L”: NG)
2
MNT1 (SHOCK)
O
Track jump detection signal output to the MD mechanism controller (IC600)
3
MNT2 (XBUSY)
O
Busy monitor signal output to the MD mechanism controller (IC600)
4
MNT3 (SLOCK)
O
Spindle servo lock status monitor signal output to the MD mechanism controller
(IC600)
5
SWDT
I
Writing serial data signal input from the MD mechanism controller (IC600)
6
SCLK
I (S)
Serial data transfer clock signal input from the MD mechanism controller (IC600)
7
XLAT
I (S)
Serial data latch pulse signal input from the MD mechanism controller (IC600)
8
SRDT
O (3)
Reading serial data signal output to the MD mechanism controller (IC600)
9
SENS
O (3)
Internal status (SENSE) output to the MD mechanism controller (IC600)
10
XRST
I (S)
Reset signal input from the MD mechanism controller (IC600) “L”: reset
11
SQSY
O
Subcode Q sync (SCOR) output to the MD mechanism controller (IC600)
“L” is output every 13.3 msec Almost all, “H” is output
12
DQSY
O
Digital In U-bit CD format subcode Q sync (SCOR) output
“L” is output every 13.3 msec Almost all, “H” is output Not used (open).
13
RECP
I
Laser power selection signal input “L”: playback mode, “H”: recording mode
Not used (fixed at “L”.).
14
XINT
O
Interrupt status output to the MD mechanism controller (IC600)
15
TX
I
Recording data output enable signal input Writing data transmission timing input
(Also serves as the magnetic head on/off output) Not used (fixed at “L”.).
16
OSCI
I
System clock signal (512 Fs = 22.5792 MHz) input terminal
17
OSCO
O
System clock signal (512 Fs = 22.5792 MHz) output terminal Not used (open)
18
XTSL
I
Input terminal for the system clock frequency setting
“L”: 45.1584 MHz, “H”: 22.5792 MHz (fixed at “L” in this set.)
19
DIN0
I
Digital audio signal input terminal when recording mode (for digital optical input)
Not used.
20
DIN1
I
Digital audio signal input terminal when recording mode (for digital optical input)
Not used.
21
DOUT
O
Digital audio signal output terminal when playback mode (for digital optical output)
22
DATAI
I
Serial data input terminal Not used (fixed at “L”.).
23
LRCKI
I
L/R sampling clock signal (44.1 kHz) input terminal Not used (fixed at “L”.).
24
XBCKI
I
Bit clock signal (2.8224 MHz) input terminal Not used (fixed at “L”.).
25
ADDT
I
Recording data input Not used (fixed at “L”.).
26
DADT
O
Playback data output to the A/D, D/A converter (IC500)
27
LRCK
O
L/R sampling clock signal (44.1 kHz) output to the A/D, D/A converter (IC500)
28
XBCK
O
Bit clock signal (2.8224 MHz) output to the A/D, D/A converter (IC500)
29
FS256
O
Clock signal (11.2896 MHz) output to the A/D, D/A converter (IC500)
30
DVDD
—
Power supply terminal (+3.3 V) (digital system)
31 – 34
A03 – A00
O
Address signal output to the D-RAM (IC201)
35
A10
O
Address signal output to the external D-RAM Not used (open).
36 – 40
A04 – A08
O
Address signal output to the D-RAM (IC201)
41
A11
O
Address signal output Not used (open).
42
DVSS
—
Ground terminal (digital system)
43
XOE
O
Output enable signal output to the D-RAM (IC201) “L” active
44
XCAS
O
Column address strobe signal output to the D-RAM (IC201) “L” active
45
A09
O
Address signal output to the D-RAM (IC201)
14
MDX-66XLP
Pin No.
Pin Name
I/O
Pin Description
46
XRAS
O
Row address strobe signal output to the D-RAM (IC201) “L” active
47
XWE
O
Write enable signal output to the D-RAM (IC201) “L” active
48
D1
I/O
49
D0
I/O
Two-way data bus with the D-RAM (IC201)
50
D2
I/O
51
D3
I/O
52
MDDT1
I (S)
Digital in PLL oscillation input from the external VCO Not used (fixed at “L”.).
53
ASYO
O
Playback EFM full-swing output terminal
54
ASYI
I (A)
Playback EFM asymmetry comparator voltage input terminal
55
AVDD
—
Power supply terminal (+3.3 V) (analog system)
56
BIAS
I (A)
Playback EFM asymmetry circuit constant current input terminal
57
RFI
I (A)
Playback EFM RF signal input from the CXA2523AR (IC100)
58
AVSS
—
Ground terminal (analog system)
59
PCO
O (3)
Phase comparison output for master clock of the recording/playback EFM master PLL
60
FILI
I (A)
Filter input for master clock of the recording/playback master PLL
61
FILO
O (A)
Filter output for master clock of the recording/playback master PLL
62
CLTV
I (A)
Internal VCO control voltage input of the recording/playback master PLL
63
PEAK
I (A)
Light amount signal (RF/ABCD) peak hold input from the CXA2523AR (IC100)
64
BOTM
I (A)
Light amount signal (RF/ABCD) bottom hold input from the CXA2523AR (IC100)
65
ABCD
I (A)
Light amount signal (ABCD) input form the CXA2523AR (IC100)
66
FE
I (A)
Focus error signal input from the CXA2523AR (IC100)
67
AUX1
I (A)
Auxiliary signal (I
3
signal/temperature signal) input from the CXA2523AR (IC100)
68
VC
I (A)
Middle point voltage (+1.65 V) input from the CXA2523AR (IC100)
69
ADIO
O (A)
Monitor output of the A/D converter input signal Not used (open).
70
AVDD
—
Power supply terminal (+3.3 V) (analog system)
71
ADRT
I (A)
A/D converter operational range upper limit voltage input terminal
(fixed at “H” in this set)
72
ADRB
I (A)
A/D converter operational range lower limit voltage input terminal
(fixed at “L” in this set)
73
AVSS
—
Ground terminal (analog system)
74
SE
I (A)
Sled error signal input from the CXA2523AR (IC100)
75
TE
I (A)
Tracking error signal input from the CXA2523AR (IC100)
76
DCHG
I (A)
Connected to the +3.3 V power supply
77
APC
I (A)
Error signal input for the laser automatic power control Not used (fixed at “H”.).
78
ADFG
I (S)
ADIP duplex FM signal (22.05 kHz ± 1 kHz) input from the CXA2523AR (IC100)
79
F0CNT
O
Filter f0 control signal output Not used (open).
80
XLRF
O
Serial data latch pulse signal output Not used (open).
81
CKRF
O
Serial data transfer clock signal output Not used (open).
82
DTRF
O
Writing serial data output Not used (open).
83
APCREF
O
Control signal output to the reference voltage generator circuit for the laser automatic
power control
84
LDDR
O
PWM signal output for the laser automatic power control Not used (open).
85
TRDR
O
Tracking servo drive PWM signal (–) output to the MPC17A36VMEL (IC300)
86
TFDR
O
Tracking servo drive PWM signal (+) output to the MPC17A36VMEL (IC300)
87
DVDD
—
Power supply terminal (+3.3 V) (digital system)
88
FFDR
O
Focus servo drive PWM signal (+) output to the MPC17A36VMEL (IC300)
89
FRDR
O
Focus servo drive PWM signal (–) output to the MPC17A36VMEL (IC300)
90
FS4
O
Clock signal (176.4 kHz) output terminal (X’tal system) Not used (open).
15
MDX-66XLP
Pin No.
Pin Name
I/O
Pin Description
91
SRDR
O
Sled servo drive PWM signal (–) output to the MPC17A36VMEL (IC300)
92
SFDR
O
Sled servo drive PWM signal (+) output to the MPC17A36VMEL (IC300)
93
SPRD
O
Spindle servo drive PWM signal (–) output to the MPC17A36VMEL (IC300)
94
SPFD
O
Spindle servo drive PWM signal (+) output to the MPC17A36VMEL (IC300)
95
FGIN
I (S)
96
TEST1
I
Input terminal for the test (fixed at “L”.)
97
TEST2
I
98
TEST3
I
99
DVSS
—
Ground terminal (digital system)
100
EFMO
O
EFM signal output terminal when recording mode Not used (open).
* I (S) stands for schmitt input, I (A) for analog input, O (3) for 3-state output, and O (A) for analog output in the column I/O.
16
MDX-66XLP
• IC600 µPD784216AGC-151-8EU (SYSTEM CONTROL)
Pin No.
Pin Name
I/O
Pin Description
1
M1
O
Elevator motor (M904) drive signal output
2
M1
O
Elevator motor (M904) drive signal output
3
M2
O
Loading motor (M903) drive signal output
4
M2
O
Loading motor (M903) drive signal output
5
MDMON
O
Mechanism deck system power control output (“H” : Power ON)
6
LES
I
Loading end sensor detection switch (S902) input
7
SES
I
Store end sensor detection switch (S903) input
8
HOME
I
Home position detection switch (S901) input (“L” : Home position)
9
VDD
—
Power supply pin (+5 V)
10
X2
—
Main system clock connecting pin (14 MHz)
11
X1
—
Main system clock connecting pin (14 MHz)
12
VSS
—
Ground pin
13
XT2
—
Sub system clock connecting pin (32.768 kHz)
14
XT1
—
Sub system clock connecting pin (32.768 kHz)
15
RESET
—
System reset input
16
BU IN
I
Backup OFF detection input (“L” : Backup OFF)
17
BUS ON
I
BUS OFF detection of SONY BUS (“H” : BUS OFF)
18
SQ SY
I
Sub code Q sync input from CXD2662R (IC200)
19
STR SW
I
STOP switch (S600) input
20
—
O
Not used.
21
CC XINT
I
Interruption status input from CXD2662R (IC200)
22
—
O
Not used.
23
AVDD
—
Power supply for A/D converter (+5 V)
24
AVREF0
—
Reference voltage for A/D converter
25
INIT
I
Initial input pin at reset (Not used in this set.)
26
TEMP
I
Thermistor connecting pin for temperature detection
27
EHS
I
Elevator height position detection input
28, 29
—
I
Connect to ground.
30 – 32
—
I
Connect to ground.
33
AVSS
—
Analog ground
34
ERR PWM
O
Error data output (Not used in this set.)
35
—
O
Not used.
36
AVREF1
—
Reference voltage for D/A converter
37, 38
—
O
Not used.
39
—
O
Not used.
40
MD SI
I
Read data signal input from CXD2662R (IC200)
41
MD SO
O
Write data signal output to CXA2523AR (IC100) and CXD2662R (IC200)
42
MD CKO
O
Serial clock signal output to CXA2523AR (IC100) and CXD2662R (IC200)
43
—
O
Not used.
44
—
O
Not used.
45
UNISI
I
Serial data input for SONY BUS
46
UNISO
O
Serial data output for SONY BUS
47
UNI CKI
I
Serial clock input for SONY BUS
48
LINKOFF
O
Link control signal output for SONY BUS (“H” : Link OFF) (Not used in this set.)
49
—
O
Not used.
50
—
I
Not used.
51, 52
D-BASS1, 2
O
Digital D-BASS select output 1, 2 (Not used in this set.)
53 – 55
—
O
Not used.
56 – 59
MNT0 – 3
I
Monitor 0 – 3 signal input from CXD2662R (IC200)
60
AGING
O
Not used.
61
AGCHK
O
Not used.
62
TFTON
O
Not used.
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