Sony MDX-61 Service Manual ▷ View online
– 35 –
Pin No.
Pin Name
I/O
Function
41
WFCK
O
WFCK clock (7.35kHz) signal output (When playback : EFM decoder PLL system,
When recoding : EFM encoder PLL system) Not used this set (OPEN)
42
GTOP
O
Opens the playback EFM frame sync protection window when “H” Not used this set (OPEN)
43
GFS
O
The playback EFM frame sync and interpolation protection timing match when “H”
Not used this set (OPEN)
44
XPLCK
O
EFM decoder PLL clock (98Fs=4.3218MHz) signal output Falling edge of the EFM PLL clock and
the EFM signal match Not used this set (OPEN)
the EFM signal match Not used this set (OPEN)
45
EFMO
O
FM signal output (When recoding) Not used this set (OPEN)
Overflow detection signal output of the internal RAM (Decoder monitor out)
46
RAOF
O
RAOF is signal generated when the 32k RAM exceeds the
±
4F jitter margin
Not used this set (OPEN)
47
MVCI
I
Oscillation input for PLL of the digital in Not used this set (Fixed at “L”)
48
TEST2
I
Test terminal input (Fixed at “L”)
49
DIPD
O (3)
Phase comparator output for PLL of the digital in When the internal VCO : Frequency ; Low
→
“H”
When the external VCO : Frequency ; Low
→
“L” Not used this set (OPEN)
50
DVSS1
–
Ground terminal (Digital system)
51
DICV
I (A)
Control voltage input terminal of the internal VCO for digital in PLL
52
DIFI
I (A)
Filter input terminal of the internal VCO for digital in PLL Not used this set (Fixed at “L”)
53
DIFO
O (A)
Filter output terminal of the internal VCO for digital in PLL Not used this set (OPEN)
54
AVDD1
–
Power supply terminal (+3.3V) (Analog system)
55
ASYO
O
Playback EFM full-swing output (L=VSS, H=VDD)
56
ASYI
I (A)
Playback EFM asymmetry comparate voltage input terminal
57
BIAS
I (A)
Playback EFM asymmetry circuit constant current input terminal
58
RFI
I (A)
Playback EFM RF signal input from CXA1981AR (IC100)
59
AVSS1
–
Ground terminal (Analog system)
60
CLTV
I (A)
VCO control voltage input terminal of the PLL for decoder PLL master clock
61
PCO
O (3)
Phase comparator output terminal of the PLL for decoder PLL master clock
62
FILI
I (A)
Filter input terminal of the PLL for decoder PLL master clock
63
FILO
O (3)
Filter output terminal of the PLL for decoder PLL master clock
64
PEAK
I (A)
Light amount peak hold signal input from CXA1981AR (IC100)
65
BOTM
I (A)
Light amount bottom hold signal input from CXA1981AR (IC100)
66
ABCD
I (A)
Light amount signal input from CXA1981AR (IC100)
67
FE
I (A)
Focus error signal input from CXA1981AR (IC100)
68
AUX1
I (A)
Sub signal input from CXA1981AR (IC100)
69
VC
I (A)
Center point voltage (1/2 VCC)
input from CXA1981AR (IC100)
70
ADIO
O (A)
Monitor output of the A/D converter input signal Not used this set (OPEN)
71
TEST3
I (A)
Test input terminal (Fixed at “L”)
72
AVDD2
–
Power supply terminal (+3.3V) (Analog system)
73
ADRT
I (A)
A/D converter action limits (upper side) voltage input (Fixed at “H”)
74
ADRB
I (A)
A/D converter action limits (lower side) voltage input (Fixed at “L”)
75
AVSS2
–
Ground terminal (Analog system)
76
SE
I (A)
Sled error signal input from CXA1981AR (IC100)
77
TE
I (A)
Tracking error signal input from CXA1981AR (IC100)
78
AUX2
I (A)
Sub signal input terminal from CXA1981AR (IC100)
– 36 –
Pin No.
Pin Name
I/O
Function
79
DCHG
I (A)
Connected to the Ground
80
APC
I (A)
Input terminal for the laser APC Not used this set (Fixed at “L”)
81
TEST1
I
Test input terminal (Fixed at “L”)
82
ADFG
I
ADIP double turned FM signal input from CXA1981AR (IC100)
(22.05kHz
±
1kHz) (TTL schmitt input)
83
TS25
I
Test input terminal (Fixed at “L”)
84
LDDR
O
Laser APC signal output to CXA1981AR (IC100)
85
TRDR
O
Tracking servo drive signal outuput (–)
86
TFDR
O
Tracking servo drive signal outuput (+)
87
FFDR
O
Focus servo drive signal output (+)
88
DVDD1
–
Power supply terminal (+3.3V) (Digital system)
89
FRDR
O
Focus servo drive signal output (–)
90
FS4
O
176.4kHz clock signal output (MCLK system) Not used this set (OPEN)
91
SRDR
O
Sled servo drive signal output (+)
92
SFDR
O
Sled servo drive signal output (–)
93
SPRD
O
Spindle servo drive signal output (+)
94
SPFD
O
Spindle servo drive signal output (–)
95
DCLO
O
Not used (OPEN)
96
DCLI
I
Not used (Fixed at “H”)
97
XDCL
O
Not used (OPEN)
98
OFTRK
O
Offtrack signal output Not used this set (OPEN)
99
COUT
O
Traverse count signal output Not used this set (OPEN)
100
DVSS2
–
Ground terminal (Digital system)
*: On I/O section
(3): 3 state output
(A): Analog output
– 37 –
Pin No.
Pin Name
I/O
Function
1
VDD
–
Power supply terminal (+3.3V)
2
SWDT
I
Write data signal input from the system controller (IC600)
3
SCK
I
Serial clock signal input from the system controller (IC600)
4
XLAT
I
Serial latch signal input from the system controller (IC600)
5
SRDT
O/Z
Read data signal output to the system controller (IC600)
6
SENSE
O/Z
Internal status (SENSE) output to the system controller (IC600)
7
SMDO
I
Serial command control mode input from the system controller (Fixed at “H”)
8
SMDI
I
Serial command control mode input from the system controller (Fixed at “H”)
9
XINT
O
Interruption status output to the system controller (IC600)
10
RCPB
I
Record/playback selection signal input (Fixed at “L”)
11
WRMN
I
Write/monitor mode selection signal input from the system controller (Fixed at “L”)
12
TX
I
Writing data transmission timing input from the system controller
Used together with the magnetic field head ON/OFF output (Fixed at “L”)
13
VSS
–
Ground terminal
14
SICK
I
Chip reserve terminal (Fixed at “H”)
15
IDSL
I
Chip reserve terminal (Fixed at “H”)
16
XILT
I
Chip reserve terminal (Fixed at “H”)
17
XRST
I
Reset signal input from the system controller (IC600) When reset : “L”
18-21
TS0-TS3
I
Test input terminal (Fixed at “L”)
22
EXIR
I
Chip reserve terminal (Fixed at “L”)
23
SASL
I
Single use the block selection “L” : ATRAC, “H” : RAM controller (Fixed at “L”)
24
SGL
I
Normally fixed at “L”, Fixed at “H” when the ATRAC or RAM controller is single used (Fixed at “L”)
25
VSS
–
Ground terminal
26
AIRCPB
O
Record/playback mode signal output terminal of the ATRAC or external audio block
Not used this set (OPEN)
27
XRQ
I/O
XRQ signal input/output terminal of the ATRAC interface
Not used this set (OPEN)
28
ADTO
I/O
Decoder data signal input/output terminal of the ATRAC
Not used this set (OPEN)
29
ADTI
I/O
Encoder data signal input/output terminal of the ATRAC
Not used this set (OPEN)
30
XALT
I/O
Data ready and XALT signal input/output terminal of the ATRAC interface
Not used this set (OPEN)
31
ACK
I/O
ACK signal input/output terminal of the ATRAC interface
Not used this set (OPEN)
32
AC2
I/O
Error data signal input/output terminal of the ATRAC interface
Not used this set (OPEN)
33
LCHST
I/O
Lch Start data signal input/output terminal of the ATRAC interface
Not used this set (OPEN)
34
EXE
I/O
EXE signal input/output terminal of the ATRAC interface
Not used this set (OPEN)
35
MUTE
I/O
MUTE signal input/output terminal of the ATRAC interface
Not used this set (OPEN)
36
OSCO
O
45.1584MHz clock oscillation output
37
OSCI
I
45.1584MHz clock oscillation input
38
VSS
–
Ground terminal
39
ATT
I/O
ATT signal input/output terminal of the ATRAC interface
Not used this set (OPEN)
40
F86
O
11.6msec timing signal output terminal of the ATRAC block
Not used this set (OPEN)
41
DOUT
O
Monitor/audio decode data signal output to the D/A converter (IC550)
42
ADIN
I
Recording data signal input Not used this set (Fixed at “L”)
43
ABCK
O
Bit clock signal output Not used this set (OPEN)
44
ALRCK
O
L/R clock signal output to the D/A converter (IC550)
45-47
SA2-SA0
O
Address signal output Not used this set (OPEN)
48, 49
A11,A10
O
Address signal output Not used this set (OPEN)
MAIN BOARD IC500 CXD2536R (SHOCK PROOF MEMORY CONTROLLER, ATRAC ENCODER/DECODER)
– 38 –
Pin No.
Pin Name
I/O
Function
50
VSS
–
Ground terminal
51
VDD
–
Power supply terminal (+3.3V)
52-55
A03-A00
O
Address signal output to the RAM (IC501)
56-60
A04-A08
O
Address signal output to the RAM (IC501)
61
XOE
O
Output enable control signal output to the RAM (IC501)
62
XCAS
O
Column address strobe signal output to the RAM (IC501)
63
VSS
–
Ground terminal
64
XCS
O
Chip select signal output Not used this set (OPEN)
65
A09
O
Address signal output to the RAM (IC501)
66
XRAS
O
Row address strobe signal output to the RAM (IC501)
67
XWE
O
Reading/Writing control signal output to the RAM (IC501)
68,69
D1,D0
I/O
RAM (IC501) data bus
70,71
D2,D3
I/O
RAM (IC501) data bus
72-74
D4-D6
I/O
Data bus Not used this set (OPEN)
75
VSS
–
Ground terminal
76
D7
I/O
Data bus Not used this set (OPEN)
77
ERR
I/O
Input /output terminal of the error (C2PO) data signal to the external RAM
Not used this set (OPEN)
78
EXTC2R
I
External RAM selection signal input for the error data writing (When “H” : External RAM)
(Fixed at “L”)
79
BUSY
O
BUSY signal output of the RAM access Not used this set (OPEN)
80
EMP
O
Empty or before the full of the ATRAC data (When DSC=ASC+1 : “H”)
Not used this set (OPEN)
81
FUL
O
Full or before the empty of the ATRAC data (When ASC=DSC+1 : “H”)
Not used this set (OPEN)
82
EQL
O
Empty of the ATRAC data (When DSC=ASC : “H”)
83
MDLK
O
Indicate the main/sub of the recording or playback data (When sub and linking : “H”,
When the main : “L”)
Not used this set (OPEN)
84
CPSY
O
Interpolation sync signal output Not used this set (OPEN)
85
CTMD0
O
DSC (Difference Signal Control) counter mode output
Not used this set (OPEN)
86
CTMD1
O
DSC (Difference Signal Control) counter mode output
Not used this set (OPEN)
87
SPO
O
System clock (512Fs=22.5792MHz) signal output to CXD2535CR (IC200) and D/A converter (IC550)
88
VSS
–
Ground terminal
89
MDSY
O
Sync detection signal output of the main data Not used this set (OPEN)
90
LRCK
I
L/R clock (44.1kHz) signal input from CXD2535CR (IC200)
91
BCK
I
Bit clock (2.8224MHz) signal input from CXD2535CR (IC200)
92
C2PO
I
C2PO (indicate the error mode of the data) signal input from CXD2535BR (IC200)
When playback : C2PO (“H”), When digital recording : D. IN-Vflag, When analog recording : “L”
93
DATA
I/O
When recording : Record audio data signal output (Not used this set)
When playback : Playback audio data signal input from CXD2535CR (IC200)
94
DIDT
I
16-bit data input terminal for the digital audio in Not used this set (Fixed at “L”)
95
DODT
O
16-bit data output terminal for the digital audio out Not used this set (OPEN)
96
DIRCPB
O
Disc drive, Record or playback mode output of the EFM encoder/decoder Not used this set (OPEN)
97
MIN
I
Defect ON/OFF selection signal input from CXD2535CR (IC200)
98
SPOSL
I
IN/OUT selection input terminal of the pin *¶ (“L” : IN, “H” : OUT) (Fixed at “H”)
99
MCK
O
Internal master clock signal output terminal of the RAM controller
100
VSS
–
Ground terminal
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